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| author | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
| commit | 8f24e0637ae113500d8bd60d80d57afcc0aa8bde (patch) | |
| tree | 4f17b423e33303a05b883cfede86c1b42714283b /board | |
| parent | 1754f50b710194f886b6f2831803d8960171a14d (diff) | |
| download | u-boot-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.gz u-boot-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.bz2 u-boot-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.zip | |
ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/lwmon5/init.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S index 6798e80985..5aade72b52 100644 --- a/board/lwmon5/init.S +++ b/board/lwmon5/init.S @@ -57,7 +57,7 @@ tlbtab: #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #endif /* TLB-entry for PCI Memory */ |