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| author | Tom Rini <trini@ti.com> | 2015-01-13 13:39:25 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-13 13:39:25 -0500 |
| commit | 5f88ed5cde04612e5b4520327b82d81a3f5493a0 (patch) | |
| tree | ae465a7b43e4a01fa4ec774f0199e86743c8d46a /board | |
| parent | 95f5c8f2269fc144fba5a21c0e9edf5311007484 (diff) | |
| parent | 657e384af630463e3c8c4ffbacd16c5e46aeb0e0 (diff) | |
| download | u-boot-5f88ed5cde04612e5b4520327b82d81a3f5493a0.tar.gz u-boot-5f88ed5cde04612e5b4520327b82d81a3f5493a0.tar.bz2 u-boot-5f88ed5cde04612e5b4520327b82d81a3f5493a0.zip | |
Merge git://git.denx.de/u-boot-x86
Diffstat (limited to 'board')
| -rw-r--r-- | board/coreboot/coreboot/Kconfig | 27 | ||||
| -rw-r--r-- | board/coreboot/coreboot/MAINTAINERS | 2 | ||||
| -rw-r--r-- | board/coreboot/coreboot/coreboot.c | 2 | ||||
| -rw-r--r-- | board/google/chromebook_link/Kconfig | 9 | ||||
| -rw-r--r-- | board/intel/crownbay/Kconfig | 1 |
5 files changed, 39 insertions, 2 deletions
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 6ca6cedf0d..981de1f071 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -9,7 +9,32 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +comment "coreboot-specific options" + config SYS_CONFIG_NAME - default "coreboot" + string "Board configuration file" + default "chromebook_link" + help + This option selects the board configuration file in include/configs/ + directory to be used to build U-Boot for coreboot. + +config DEFAULT_DEVICE_TREE + string "Board Device Tree Source (dts) file" + default "chromebook_link" + help + This option selects the board Device Tree Source (dts) file in + arch/x86/dts/ directory to be used to build U-Boot for coreboot. + +config SYS_CAR_ADDR + hex "Board specific Cache-As-RAM (CAR) address" + default 0x19200000 + help + This option specifies the board specific Cache-As-RAM (CAR) address. + +config SYS_CAR_SIZE + hex "Board specific Cache-As-RAM (CAR) size" + default 0x4000 + help + This option specifies the board specific Cache-As-RAM (CAR) size. endif diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 6ce66f551f..2736aa0282 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -2,5 +2,5 @@ COREBOOT BOARD M: Simon Glass <sjg@chromium.org> S: Maintained F: board/coreboot/coreboot/ -F: include/configs/coreboot.h +F: include/configs/chromebook_link.h F: configs/coreboot-x86_defconfig diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 154faf6239..e076ea69cf 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -10,8 +10,10 @@ int arch_early_init_r(void) { +#ifdef CONFIG_CROS_EC if (cros_ec_board_init()) return -1; +#endif return 0; } diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 7f79fd206f..33a31f311f 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -14,6 +14,7 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 @@ -29,4 +30,12 @@ config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC" default y +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index 4709f9b55d..762663a001 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -14,6 +14,7 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select X86_RESET_VECTOR select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024 |