powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200

These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>

27 files changed, 0 insertions, 3183 deletions

diff --git a/board/esd/cpci5200/Kconfig b/board/esd/cpci5200/Kconfig
deleted file mode 100644
index ddd9418d3d..0000000000
--- a/board/esd/cpci5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI5200
-
-config SYS_BOARD
-	default "cpci5200"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "cpci5200"
-
-endif
diff --git a/board/esd/cpci5200/MAINTAINERS b/board/esd/cpci5200/MAINTAINERS
deleted file mode 100644
index 184d3cc428..0000000000
--- a/board/esd/cpci5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCI5200 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/cpci5200/
-F:	include/configs/cpci5200.h
-F:	configs/cpci5200_defconfig
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
deleted file mode 100644
index 8421f54869..0000000000
--- a/board/esd/cpci5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD  = ../common/xilinx_jtag/lenval.o \
-#	  ../common/xilinx_jtag/micro.o \
-#	  ../common/xilinx_jtag/ports.o
-
-# obj-y	= cpci5200.o flash.o $(CPLD)
-obj-y	= cpci5200.o strataflash.o
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
deleted file mode 100644
index 8bded0bbca..0000000000
--- a/board/esd/cpci5200/cpci5200.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * cpci5200.c - main board support/init for the esd cpci5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_ata_reset(void);
-
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-	} else {
-#if 0
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-#else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
-#endif
-	}
-
-#if 0
-	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(0);
-#endif
-	/* set SDRAM CS1 size according to the amount of RAM found */
-
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
-
-	init_ata_reset();
-	return (dramsize);
-}
-
-int checkboard(void)
-{
-	puts("Board: esd CPCI5200 (cpci5200)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x02000000) {
-		/* adjust mapping */
-		*(vu_long *) MPC5XXX_BOOTCS_START =
-		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *) MPC5XXX_BOOTCS_STOP =
-		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-	}
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6	0x40000000UL
-#define GPIO_USB0       0x00010000UL
-#define GPIO_USB9       0x08000000UL
-#define GPIO_USB9S      0x00080000UL
-
-void init_ata_reset(void)
-{
-	debug("init_ata_reset\n");
-
-	/* Configure GPIO_WU6 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
-	__asm__ volatile ("sync");
-
-	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
-		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
-		__asm__ volatile ("sync");
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	int i;
-	volatile unsigned long *ptr;
-
-	addr = simple_strtol(argv[1], NULL, 16);
-	size = simple_strtol(argv[2], NULL, 16);
-
-	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
-	while (1) {
-		ptr = (volatile unsigned long *)addr;
-		for (i = 0; i < (size >> 2); i++) {
-			*ptr++ = i;
-		}
-
-		/* Abort if ctrl-c was pressed */
-		if (ctrlc()) {
-			puts("\nAbort\n");
-			return 0;
-		}
-		putc('.');
-	}
-	return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
-	   "Write some data to pcibus",
-	   "<addr> <size>\n"
-	   ""
-);
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
deleted file mode 100644
index 63a403231d..0000000000
--- a/board/esd/cpci5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1	/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x705f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
deleted file mode 100644
index 7dc2e58c12..0000000000
--- a/board/esd/cpci5200/strataflash.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-#undef  DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI			0x98
-#define FLASH_CMD_READ_ID		0x90
-#define FLASH_CMD_RESET			0xff
-#define FLASH_CMD_BLOCK_ERASE		0x20
-#define FLASH_CMD_ERASE_CONFIRM		0xD0
-#define FLASH_CMD_WRITE			0x40
-#define FLASH_CMD_PROTECT		0x60
-#define FLASH_CMD_PROTECT_SET		0x01
-#define FLASH_CMD_PROTECT_CLEAR		0xD0
-#define FLASH_CMD_CLEAR_STATUS		0x50
-#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
-
-#define FLASH_STATUS_DONE		0x80
-#define FLASH_STATUS_ESS		0x40
-#define FLASH_STATUS_ECLBS		0x20
-#define FLASH_STATUS_PSLBS		0x10
-#define FLASH_STATUS_VPENS		0x08
-#define FLASH_STATUS_PSS		0x04
-#define FLASH_STATUS_DPS		0x02
-#define FLASH_STATUS_R			0x01
-#define FLASH_STATUS_PROTECT		0x01
-
-#define FLASH_OFFSET_CFI		0x55
-#define FLASH_OFFSET_CFI_RESP		0x10
-#define FLASH_OFFSET_WTOUT		0x1F
-#define FLASH_OFFSET_WBTOUT             0x20
-#define FLASH_OFFSET_ETOUT		0x21
-#define FLASH_OFFSET_CETOUT             0x22
-#define FLASH_OFFSET_WMAX_TOUT		0x23
-#define FLASH_OFFSET_WBMAX_TOUT         0x24
-#define FLASH_OFFSET_EMAX_TOUT		0x25
-#define FLASH_OFFSET_CEMAX_TOUT         0x26
-#define FLASH_OFFSET_SIZE		0x27
-#define FLASH_OFFSET_INTERFACE          0x28
-#define FLASH_OFFSET_BUFFER_SIZE        0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
-#define FLASH_OFFSET_ERASE_REGIONS	0x2D
-#define FLASH_OFFSET_PROTECT		0x02
-#define FLASH_OFFSET_USER_PROTECTION    0x85
-#define FLASH_OFFSET_INTEL_PROTECTION   0x81
-
-#define FLASH_MAN_CFI			0x01000000
-
-typedef union {
-	unsigned char c;
-	unsigned short w;
-	unsigned long l;
-} cfiword_t;
-
-typedef union {
-	unsigned char *cp;
-	unsigned short *wp;
-	unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
-			    uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset,
-			 uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size(ulong base, int banknum);
-static int flash_write_cfiword(flash_info_t * info, ulong dest,
-			       cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector,
-				   ulong tout, char *prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
-				 int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
-{
-	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
-}
-
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
-	uchar *cp;
-	cp = flash_make_addr(info, 0, offset);
-	return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
-	uchar *addr;
-
-	addr = flash_make_addr(info, sect, offset);
-	return ((addr[(2 * info->portwidth) - 1] << 8) |
-		addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
-	uchar *addr;
-
-	addr = flash_make_addr(info, sect, offset);
-	return ((addr[(2 * info->portwidth) - 1] << 24) |
-		(addr[(info->portwidth) - 1] << 16) |
-		(addr[(4 * info->portwidth) - 1] << 8) |
-		addr[(3 * info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init(void)
-{
-	unsigned long size;
-	int i;
-	unsigned long address;
-
-	/* The flash is positioned back to back, with the demultiplexing of the chip
-	 * based on the A24 address line.
-	 *
-	 */
-
-	address = CONFIG_SYS_FLASH_BASE;
-	size = 0;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		size += flash_info[i].size = flash_get_size(address, i);
-		address += CONFIG_SYS_FLASH_INCREMENT;
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf
-			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-			     i, flash_info[0].size, flash_info[i].size << 20);
-		}
-	}
-
-#if 0				/* test-only */
-	/* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-	for (i = 0;
-	     flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
-	     i++)
-		(void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
-	return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	int rcode = 0;
-	int prot;
-	int sect;
-
-	if (info->flash_id != FLASH_MAN_CFI) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-	if ((s_first < 0) || (s_first > s_last)) {
-		printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	} else {
-		printf("\n");
-	}
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
-			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
-			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
-			if (flash_full_status_check
-			    (info, sect, info->erase_blk_tout, "erase")) {
-				rcode = 1;
-			} else
-				printf(".");
-		}
-	}
-	printf(" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id != FLASH_MAN_CFI) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	printf("CFI conformant FLASH (%d x %d)",
-	       (info->portwidth << 3), (info->chipwidth << 3));
-	printf("  Size: %ld MB in %d Sectors\n",
-	       info->size >> 20, info->sector_count);
-	printf
-	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
-	     info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
-	     info->buffer_size);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n");
-		printf(" %08lX%5s",
-		       info->start[i], info->protect[i] ? " (RO)" : " ");
-	}
-	printf("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong wp;
-	ulong cp;
-	int aln;
-	cfiword_t cword;
-	int i, rc;
-
-	/* get lower aligned address */
-	wp = (addr & ~(info->portwidth - 1));
-
-	/* handle unaligned start */
-	if ((aln = addr - wp) != 0) {
-		cword.l = 0;
-		cp = wp;
-		for (i = 0; i < aln; ++i, ++cp)
-			flash_add_byte(info, &cword, (*(uchar *) cp));
-
-		for (; (i < info->portwidth) && (cnt > 0); i++) {
-			flash_add_byte(info, &cword, *src++);
-			cnt--;
-			cp++;
-		}
-		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
-			flash_add_byte(info, &cword, (*(uchar *) cp));
-		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
-			return rc;
-		wp = cp;
-	}
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-	while (cnt >= info->portwidth) {
-		i = info->buffer_size > cnt ? cnt : info->buffer_size;
-		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
-			return rc;
-		wp += i;
-		src += i;
-		cnt -= i;
-	}
-#else
-	/* handle the aligned part */
-	while (cnt >= info->portwidth) {
-		cword.l = 0;
-		for (i = 0; i < info->portwidth; i++) {
-			flash_add_byte(info, &cword, *src++);
-		}
-		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
-			return rc;
-		wp += info->portwidth;
-		cnt -= info->portwidth;
-	}
-#endif				/* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	cword.l = 0;
-	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
-		flash_add_byte(info, &cword, *src++);
-		--cnt;
-	}
-	for (; i < info->portwidth; ++i, ++cp) {
-		flash_add_byte(info, &cword, (*(uchar *) cp));
-	}
-
-	return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t * info, long sector, int prot)
-{
-	int retcode = 0;
-
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
-	if (prot)
-		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
-	else
-		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
-	if ((retcode =
-	     flash_full_status_check(info, sector, info->erase_blk_tout,
-				     prot ? "protect" : "unprotect")) == 0) {
-
-		info->protect[sector] = prot;
-		/* Intel's unprotect unprotects all locking */
-		if (prot == 0) {
-			int i;
-			for (i = 0; i < info->sector_count; i++) {
-				if (info->protect[i])
-					flash_real_protect(info, i, 1);
-			}
-		}
-	}
-
-	return retcode;
-}
-
-/*-----------------------------------------------------------------------
- *  wait for XSR.7 to be set. Time out with an error if it does not.
- *  This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
-			      char *prompt)
-{
-	ulong start;
-
-	/* Wait for command completion */
-	start = get_timer(0);
-	while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
-		if (get_timer(start) > info->erase_blk_tout) {
-			printf("Flash %s timeout at address %lx\n", prompt,
-			       info->start[sector]);
-			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-			return ERR_TIMOUT;
-		}
-	}
-	return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector,
-				   ulong tout, char *prompt)
-{
-	int retcode;
-	retcode = flash_status_check(info, sector, tout, prompt);
-	if ((retcode == ERR_OK)
-	    && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
-		retcode = ERR_INVAL;
-		printf("Flash %s error at address %lx\n", prompt,
-		       info->start[sector]);
-		if (flash_isset
-		    (info, sector, 0,
-		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
-			printf("Command Sequence Error.\n");
-		} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
-			printf("Block Erase Error.\n");
-			retcode = ERR_NOT_ERASED;
-		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
-			printf("Locking Error\n");
-		}
-		if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
-			printf("Block locked.\n");
-			retcode = ERR_PROTECTED;
-		}
-		if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
-			printf("Vpp Low Error.\n");
-	}
-	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-	return retcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
-{
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		cword->c = c;
-		break;
-	case FLASH_CFI_16BIT:
-		cword->w = (cword->w << 8) | c;
-		break;
-	case FLASH_CFI_32BIT:
-		cword->l = (cword->l << 8) | c;
-	}
-}
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
-{
-	int i;
-	uchar *cp = (uchar *) cmdbuf;
-	for (i = 0; i < info->portwidth; i++)
-		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
-			    uchar cmd)
-{
-
-	volatile cfiptr_t addr;
-	cfiword_t cword;
-	addr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		*addr.cp = cword.c;
-		break;
-	case FLASH_CFI_16BIT:
-		*addr.wp = cword.w;
-		break;
-	case FLASH_CFI_32BIT:
-		*addr.lp = cword.l;
-		break;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-	cfiptr_t cptr;
-	cfiword_t cword;
-	int retval;
-	cptr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		retval = (cptr.cp[0] == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		retval = (cptr.wp[0] == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		retval = (cptr.lp[0] == cword.l);
-		break;
-	default:
-		retval = 0;
-		break;
-	}
-	return retval;
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-	cfiptr_t cptr;
-	cfiword_t cword;
-	int retval;
-	cptr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		retval = ((cptr.cp[0] & cword.c) == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		retval = ((cptr.wp[0] & cword.w) == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		retval = ((cptr.lp[0] & cword.l) == cword.l);
-		break;
-	default:
-		retval = 0;
-		break;
-	}
-	return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
-	for (info->portwidth = FLASH_CFI_8BIT;
-	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
-		for (info->chipwidth = FLASH_CFI_BY8;
-		     info->chipwidth <= info->portwidth;
-		     info->chipwidth <<= 1) {
-			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
-					FLASH_CMD_CFI);
-			if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
-			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
-					     'R')
-			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
-					     'Y'))
-				return 1;
-		}
-	}
-	return 0;
-}
-
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size(ulong base, int banknum)
-{
-	flash_info_t *info = &flash_info[banknum];
-	int i, j;
-	int sect_cnt;
-	unsigned long sector;
-	unsigned long tmp;
-	int size_ratio = 0;
-	uchar num_erase_regions;
-	int erase_region_size;
-	int erase_region_count;
-
-	info->start[0] = base;
-#if 0
-	invalidate_dcache_range(base, base + 0x400);
-#endif
-	if (flash_detect_cfi(info)) {
-
-		size_ratio = info->portwidth / info->chipwidth;
-		num_erase_regions =
-		    flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-
-		sect_cnt = 0;
-		sector = base;
-		for (i = 0; i < num_erase_regions; i++) {
-			if (i > NUM_ERASE_REGIONS) {
-				printf("%d erase regions found, only %d used\n",
-				       num_erase_regions, NUM_ERASE_REGIONS);
-				break;
-			}
-			tmp =
-			    flash_read_long(info, 0,
-					    FLASH_OFFSET_ERASE_REGIONS);
-			erase_region_size =
-			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
-			tmp >>= 16;
-			erase_region_count = (tmp & 0xffff) + 1;
-			for (j = 0; j < erase_region_count; j++) {
-				info->start[sect_cnt] = sector;
-				sector += (erase_region_size * size_ratio);
-				info->protect[sect_cnt] =
-				    flash_isset(info, sect_cnt,
-						FLASH_OFFSET_PROTECT,
-						FLASH_STATUS_PROTECT);
-				sect_cnt++;
-			}
-		}
-
-		info->sector_count = sect_cnt;
-		/* multiply the size by the number of chips */
-		info->size =
-		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
-		    size_ratio;
-		info->buffer_size =
-		    (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
-		info->erase_blk_tout =
-		    (tmp *
-		     (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
-		info->buffer_write_tout =
-		    (tmp *
-		     (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
-		info->write_tout =
-		    (tmp *
-		     (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
-		    1000;
-		info->flash_id = FLASH_MAN_CFI;
-	}
-
-	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-#ifdef DEBUG_FLASH
-	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
-#endif
-#ifdef DEBUG_FLASH
-	printf("found %d erase regions\n", num_erase_regions);
-#endif
-#ifdef DEBUG_FLASH
-	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
-#endif
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
-{
-
-	cfiptr_t cptr;
-	int flag;
-
-	cptr.cp = (uchar *)dest;
-
-	/* Check if Flash is (sufficiently) erased */
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		flag = ((cptr.cp[0] & cword.c) == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		flag = ((cptr.wp[0] & cword.w) == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		flag = ((cptr.lp[0] & cword.l) == cword.l);
-		break;
-	default:
-		return 2;
-	}
-	if (!flag)
-		return 2;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
-	switch (info->portwidth) {
-	case FLASH_CFI_8BIT:
-		cptr.cp[0] = cword.c;
-		break;
-	case FLASH_CFI_16BIT:
-		cptr.wp[0] = cword.w;
-		break;
-	case FLASH_CFI_32BIT:
-		cptr.lp[0] = cword.l;
-		break;
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t * info, ulong addr)
-{
-	int sector;
-	for (sector = info->sector_count - 1; sector >= 0; sector--) {
-		if (addr >= info->start[sector])
-			break;
-	}
-	return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
-				 int len)
-{
-
-	int sector;
-	int cnt;
-	int retcode;
-	volatile cfiptr_t src;
-	volatile cfiptr_t dst;
-
-	src.cp = cp;
-	dst.cp = (uchar *) dest;
-	sector = find_sector(info, dest);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
-	if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
-					  "write to buffer")) == ERR_OK) {
-		switch (info->portwidth) {
-		case FLASH_CFI_8BIT:
-			cnt = len;
-			break;
-		case FLASH_CFI_16BIT:
-			cnt = len >> 1;
-			break;
-		case FLASH_CFI_32BIT:
-			cnt = len >> 2;
-			break;
-		default:
-			return ERR_INVAL;
-			break;
-		}
-		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
-		while (cnt-- > 0) {
-			switch (info->portwidth) {
-			case FLASH_CFI_8BIT:
-				*dst.cp++ = *src.cp++;
-				break;
-			case FLASH_CFI_16BIT:
-				*dst.wp++ = *src.wp++;
-				break;
-			case FLASH_CFI_32BIT:
-				*dst.lp++ = *src.lp++;
-				break;
-			default:
-				return ERR_INVAL;
-				break;
-			}
-		}
-		flash_write_cmd(info, sector, 0,
-				FLASH_CMD_WRITE_BUFFER_CONFIRM);
-		retcode =
-		    flash_full_status_check(info, sector,
-					    info->buffer_write_tout,
-					    "buffer write");
-	}
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	return retcode;
-}
-#endif				/* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/mecp5200/Kconfig b/board/esd/mecp5200/Kconfig
deleted file mode 100644
index cfd5307751..0000000000
--- a/board/esd/mecp5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5200
-
-config SYS_BOARD
-	default "mecp5200"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "mecp5200"
-
-endif
diff --git a/board/esd/mecp5200/MAINTAINERS b/board/esd/mecp5200/MAINTAINERS
deleted file mode 100644
index 05b78240ac..0000000000
--- a/board/esd/mecp5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5200 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/mecp5200/
-F:	include/configs/mecp5200.h
-F:	configs/mecp5200_defconfig
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
deleted file mode 100644
index 3d66c9f53d..0000000000
--- a/board/esd/mecp5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= mecp5200.o
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
deleted file mode 100644
index 17a70a9ff6..0000000000
--- a/board/esd/mecp5200/mecp5200.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-	} else {
-#if 0
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-#else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
-#endif
-	}
-
-#if 0
-	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(0);
-#endif
-	/* set SDRAM CS1 size according to the amount of RAM found */
-
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
-
-	init_power_switch();
-	return (dramsize);
-}
-
-int checkboard(void)
-{
-	puts("Board: esd CPX CPU5200 (mecp5200)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == CONFIG_SYS_FLASH_SIZE) {
-		/* adjust mapping */
-		*(vu_long *) MPC5XXX_BOOTCS_START =
-		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *) MPC5XXX_BOOTCS_STOP =
-		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC1_4	0x01000000UL
-
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset)
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	else
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6	0x40000000UL
-#define GPIO_USB0       0x00010000UL
-#define GPIO_USB9       0x08000000UL
-#define GPIO_USB9S      0x00080000UL
-
-void init_power_switch(void)
-{
-	debug("init_power_switch\n");
-
-	/* Configure GPIO_WU6 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
-	__asm__ volatile ("sync");
-
-	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
-		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
-		__asm__ volatile ("sync");
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
deleted file mode 100644
index 63a403231d..0000000000
--- a/board/esd/mecp5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1	/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x705f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/esd/pf5200/Kconfig b/board/esd/pf5200/Kconfig
deleted file mode 100644
index c596e7a66c..0000000000
--- a/board/esd/pf5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PF5200
-
-config SYS_BOARD
-	default "pf5200"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "pf5200"
-
-endif
diff --git a/board/esd/pf5200/MAINTAINERS b/board/esd/pf5200/MAINTAINERS
deleted file mode 100644
index b6e624e074..0000000000
--- a/board/esd/pf5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PF5200 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/pf5200/
-F:	include/configs/pf5200.h
-F:	configs/pf5200_defconfig
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
deleted file mode 100644
index a54289c073..0000000000
--- a/board/esd/pf5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD  = ../common/xilinx_jtag/lenval.o \
-#	  ../common/xilinx_jtag/micro.o \
-#	  ../common/xilinx_jtag/ports.o
-
-# obj-y	= pf5200.o flash.o $(CPLD)
-obj-y	= pf5200.o flash.o
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
deleted file mode 100644
index e1b13bfc44..0000000000
--- a/board/esd/pf5200/flash.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-
-#define FLASH_ID_MASK           0x00FF
-
-#define FPW                     FLASH_PORT_WIDTH
-#define FPWV                    FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1            0x0555
-#define FLASH_CYCLE2            0x0aaa
-#define FLASH_ID1               0x00
-#define FLASH_ID2               0x01
-#define FLASH_ID3               0x0E
-#define FLASH_ID4               0x0F
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV * addr, flash_info_t * info);
-static void flash_reset(flash_info_t * info);
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init(void)
-{
-	unsigned long size = 0;
-	int i = 0;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(uint, ulong, ulong);
-
-	ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
-	flash_preinit();
-
-	/* There is only ONE FLASH device */
-	memset(&flash_info[i], 0, sizeof(flash_info_t));
-	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
-	size += flash_info[i].size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef  CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-		      flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
-	return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t * info) {
-	FPWV *base = (FPWV *) (info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
-	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base) {
-	int i;
-	flash_info_t *info;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		info = &flash_info[i];
-		if ((info->size) && (info->start[0] <= base)
-		    && (base <= info->start[0] + info->size - 1)) {
-			break;
-		}
-	}
-	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info(flash_info_t * info) {
-	int i;
-	char *fmt;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf("AMD ");
-		break;
-	default:
-		printf("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMLV256U:
-		fmt = "29LV256M (256 Mbit)\n";
-		break;
-	default:
-		fmt = "Unknown Chip Type\n";
-		break;
-	}
-
-	printf(fmt);
-	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20,
-	       info->sector_count);
-	printf("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; ++i) {
-		ulong size;
-		int erased;
-		ulong *flash = (unsigned long *)info->start[i];
-
-		if ((i % 5) == 0) {
-			printf("\n   ");
-		}
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size =
-		    (i !=
-		     (info->sector_count - 1)) ? (info->start[i + 1] -
-						  info->start[i]) >> 2 : (info->
-									  start
-									  [0] +
-									  info->
-									  size -
-									  info->
-									  start
-									  [i])
-		    >> 2;
-
-		for (flash = (unsigned long *)info->start[i], erased = 1;
-		     (flash != (unsigned long *)info->start[i] + size)
-		     && erased; flash++) {
-			erased = *flash == ~0x0UL;
-		}
-		printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
-		       info->protect[i] ? "(RO)" : "    ");
-	}
-
-	printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size(FPWV * addr, flash_info_t * info) {
-	int i;
-
-	/* Write auto select command: read Manufacturer ID                     */
-	/* Write auto select command sequence and test FLASH answer            */
-	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD        */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.         */
-	/* This works for any bus width and any FLASH device width.            */
-	udelay(100);
-	switch (addr[FLASH_ID1] & 0x00ff) {
-	case (uchar) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	default:
-		printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus.     */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		switch ((FPW) addr[FLASH_ID2]) {
-		case (FPW) AMD_ID_MIRROR:
-			/* MIRROR BIT FLASH, read more ID bytes */
-			if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
-			    && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
-				/* attention: only the first 16 MB will be used in u-boot */
-				info->flash_id += FLASH_AMLV256U;
-				info->sector_count = 512;
-				info->size = 0x02000000;
-				for (i = 0; i < info->sector_count; i++) {
-					info->start[i] =
-					    (ulong) addr + 0x10000 * i;
-				}
-				break;
-			}
-			/* fall thru to here ! */
-		default:
-			printf("unknown AMD device=%x %x %x",
-			       (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
-			       (FPW) addr[FLASH_ID4]);
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0x800000;
-			break;
-		}
-
-		/* Put FLASH back in read mode */
-		flash_reset(info);
-	}
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last) {
-	FPWV *addr;
-	int flag, prot, sect;
-	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf("- missing\n");
-		} else {
-			printf("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMLV256U:
-		break;
-	case FLASH_UNKNOWN:
-	default:
-		printf("Can't erase unknown flash type %08lx - aborted\n",
-		       info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	} else {
-		printf("\n");
-	}
-
-	last = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
-		if (info->protect[sect] != 0) {	/* protected, skip it */
-			continue;
-		}
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *) (info->start[sect]);
-		if (intel) {
-			*addr = (FPW) 0x00500050;	/* clear status register */
-			*addr = (FPW) 0x00200020;	/* erase setup */
-			*addr = (FPW) 0x00D000D0;	/* erase confirm */
-		} else {
-			/* must be AMD style if not Intel */
-			FPWV *base;	/* first address in bank */
-
-			base = (FPWV *) (info->start[0]);
-			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-			base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
-			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-			*addr = (FPW) 0x00300030;	/* erase sector */
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag) {
-			enable_interrupts();
-		}
-		start = get_timer(0);
-
-		/* wait at least 50us for AMD, 80us for Intel. */
-		/* Let's wait 1 ms.                            */
-		udelay(1000);
-
-		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf("Timeout\n");
-				if (intel) {
-					/* suspend erase        */
-					*addr = (FPW) 0x00B000B0;
-				}
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;	/* failed */
-				break;
-			}
-			/* show that we're waiting */
-			if ((get_timer(last)) > CONFIG_SYS_HZ) {
-				/* every second */
-				putc('.');
-				last = get_timer(0);
-			}
-		}
-		/* show that we're waiting */
-		if ((get_timer(last)) > CONFIG_SYS_HZ) {
-			/* every second */
-			putc('.');
-			last = get_timer(0);
-		}
-		flash_reset(info);	/* reset to read mode */
-	}
-	printf(" done\n");
-	return (rcode);
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
-	int bytes;		/* number of bytes to program in current word         */
-	int left;		/* number of bytes left to program                    */
-	int i, res;
-
-	for (left = cnt, res = 0;
-	     left > 0 && res == 0;
-	     addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-		bytes = addr & (sizeof(data) - 1);
-		addr &= ~(sizeof(data) - 1);
-
-		/* combine source and destination data so can program
-		 * an entire word of 16 or 32 bits
-		 */
-		for (i = 0; i < sizeof(data); i++) {
-			data <<= 8;
-			if (i < bytes || i - bytes >= left)
-				data += *((uchar *) addr + i);
-			else
-				data += *src++;
-		}
-
-		/* write one word to the flash */
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			res = write_word_amd(info, (FPWV *) addr, data);
-			break;
-		default:
-			/* unknown flash type, error! */
-			printf("missing or unknown FLASH type\n");
-			res = 1;	/* not really a timeout, but gives error */
-			break;
-		}
-	}
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
-	ulong start;
-	int flag;
-	int res = 0;		/* result, assume success       */
-	FPWV *base;		/* first address in flash bank  */
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-	base = (FPWV *) (info->start[0]);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data   */
-
-	/* re-enable interrupts if necessary */
-	if (flag) {
-		enable_interrupts();
-	}
-	start = get_timer(0);
-
-	/* data polling for D7 */
-	while (res == 0
-	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dest = (FPW) 0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-	return (res);
-}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
deleted file mode 100644
index 63a403231d..0000000000
--- a/board/esd/pf5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1	/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x705f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
deleted file mode 100644
index 7a9ed229ef..0000000000
--- a/board/esd/pf5200/pf5200.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL =
-	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-	} else {
-#if 0
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
-#else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
-		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
-		/* let SDRAM CS1 start right after CS0 */
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
-#endif
-	}
-
-#if 0
-	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(0);
-#endif
-	/* set SDRAM CS1 size according to the amount of RAM found */
-
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
-
-	init_power_switch();
-	return (dramsize);
-}
-
-int checkboard(void)
-{
-	puts("Board: esd ParaFinder (pf5200)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x02000000) {
-		/* adjust mapping */
-		*(vu_long *) MPC5XXX_BOOTCS_START =
-		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *) MPC5XXX_BOOTCS_STOP =
-		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-	}
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6	0x40000000UL
-#define GPIO_USB0       0x00010000UL
-#define GPIO_USB9       0x08000000UL
-#define GPIO_USB9S      0x00080000UL
-
-void init_power_switch(void)
-{
-	debug("init_power_switch\n");
-
-	/* Configure GPIO_WU6 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
-	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
-	__asm__ volatile ("sync");
-
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
-	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
-	__asm__ volatile ("sync");
-
-	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
-		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
-		__asm__ volatile ("sync");
-	}
-	*(vu_char *) CONFIG_SYS_CS1_START = 0x02;	/* Red Power LED on */
-	__asm__ volatile ("sync");
-
-	*(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
-	__asm__ volatile ("sync");
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void power_set_reset(int power)
-{
-	debug("ide_set_reset(%d)\n", power);
-
-	if (power) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
-		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
-		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
-		    0) {
-			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
-			    GPIO_USB0;
-		}
-
-	}
-}
-
-int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	power_set_reset(1);
-	return (0);
-}
-
-U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
-
-int phypower(int flag)
-{
-	u32 addr;
-	vu_long *reg;
-	int status;
-	pci_dev_t dev;
-
-	dev = PCI_BDF(0, 0x18, 0);
-	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
-	if (status == 0) {
-		reg = (vu_long *) (addr + 0x00000040);
-		*reg |= 0x40000000;
-		__asm__ volatile ("sync");
-
-		reg = (vu_long *) (addr + 0x001000c);
-		*reg |= 0x20000000;
-		__asm__ volatile ("sync");
-
-		reg = (vu_long *) (addr + 0x0010004);
-		if (flag != 0) {
-			*reg &= ~0x20000000;
-		} else {
-			*reg |= 0x20000000;
-		}
-		__asm__ volatile ("sync");
-	}
-	return (status);
-}
-
-int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argv[1][0] == '0')
-		(void)phypower(0);
-	else
-		(void)phypower(1);
-
-	return (0);
-}
-
-U_BOOT_CMD(phypower, 2, 2, do_phypower,
-	   "Switch power of ethernet phy", "");
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	int i;
-	volatile unsigned long *ptr;
-
-	addr = simple_strtol(argv[1], NULL, 16);
-	size = simple_strtol(argv[2], NULL, 16);
-
-	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
-	while (1) {
-		ptr = (volatile unsigned long *)addr;
-		for (i = 0; i < (size >> 2); i++) {
-			*ptr++ = i;
-		}
-
-		/* Abort if ctrl-c was pressed */
-		if (ctrlc()) {
-			puts("\nAbort\n");
-			return 0;
-		}
-		putc('.');
-	}
-	return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
-	"Write some data to pcibus",
-	"<addr> <size>\n"
-	""
-);
diff --git a/board/icecube/Kconfig b/board/icecube/Kconfig
deleted file mode 100644
index e5b2153911..0000000000
--- a/board/icecube/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ICECUBE
-
-config SYS_BOARD
-	default "icecube"
-
-config SYS_CONFIG_NAME
-	default "IceCube"
-
-endif
diff --git a/board/icecube/MAINTAINERS b/board/icecube/MAINTAINERS
deleted file mode 100644
index 8a24eb4699..0000000000
--- a/board/icecube/MAINTAINERS
+++ /dev/null
@@ -1,21 +0,0 @@
-ICECUBE BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/icecube/
-F:	include/configs/IceCube.h
-F:	configs/icecube_5200_defconfig
-
-ICECUBE_5200_DDR BOARD
-#M:	-
-S:	Maintained
-F:	configs/icecube_5200_DDR_defconfig
-F:	configs/icecube_5200_DDR_LOWBOOT_defconfig
-F:	configs/icecube_5200_DDR_LOWBOOT08_defconfig
-F:	configs/icecube_5200_LOWBOOT_defconfig
-F:	configs/icecube_5200_LOWBOOT08_defconfig
-F:	configs/Lite5200_defconfig
-F:	configs/Lite5200_LOWBOOT_defconfig
-F:	configs/Lite5200_LOWBOOT08_defconfig
-F:	configs/lite5200b_defconfig
-F:	configs/lite5200b_LOWBOOT_defconfig
-F:	configs/lite5200b_PM_defconfig
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
deleted file mode 100644
index c3c2cd1c3e..0000000000
--- a/board/icecube/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= icecube.o flash.o
diff --git a/board/icecube/README b/board/icecube/README
deleted file mode 100644
index 5252bc9767..0000000000
--- a/board/icecube/README
+++ /dev/null
@@ -1,13 +0,0 @@
----------------------------------------------------------------------------
-Build target                Flash address | BDI "go" command | Reset Vector
----------------------------------------------------------------------------
-Lite5200                     0xFFF00000   |    0xFFF00100    |   0xFFF00100
-Lite5200_LOWBOOT             0xFF000000   |    0xFF000100    |   0x00000100
-Lite5200_LOWBOOT08           0xFF800000   |    0xFF800100    |   0x00000100
-icecube_5200                 0xFFF00000   |    0xFFF00100    |   0xFFF00100
-icecube_5200_LOWBOOT         0xFF000000   |    0xFF000100    |   0x00000100
-icecube_5200_LOWBOOT08       0xFF800000   |    0xFF800100    |   0x00000100
-icecube_5200_DDR             0xFFF00000   |    0xFFF00100    |   0xFFF00100
-icecube_5200_DDR_LOWBOOT     0xFF800000   |    0xFF800100    |   0x00000100
-icecube_5200_DDR_LOWBOOT08   0xFF800000   |    0xFF800100    |   0x00000100
----------------------------------------------------------------------------
diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power
deleted file mode 100644
index 5b04fbba72..0000000000
--- a/board/icecube/README.Lite5200B_low_power
+++ /dev/null
@@ -1,22 +0,0 @@
-Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
-----------------------------------------------------------
-
-Low-power mode as described in Lite5200B User's Manual, means that
-with support of MC68HLC908QT1 microcontroller (refered to as QT),
-everything but the SDRAM can be powered down. This brings
-maximum power saving, while one can still restore previous state
-quickly.
-
-Quick overview where U-Boot comes into the picture:
-- OS saves device states
-- OS saves wakeup handler address to physical 0x0, puts SDRAM into
-  self-refresh and signals to QT, it should power down the board
-- / board is sleeping here /
-- someone presses SW4 (connected to QT)
-- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
-  so get SDRAM out of self-refresh and transfer control to OS
-  wakeup handler
-- OS restores device states
-
-This was tested on Linux with USB and Ethernet in use. Adding
-support for other devices is an OS issue.
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
deleted file mode 100644
index a044e8f24a..0000000000
--- a/board/icecube/flash.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#ifndef CONFIG_FLASH_CFI_DRIVER
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- *        has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFFFF
-#else
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define	FLASH_ID_MASK	0xFF
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH_CYCLE1	0x0555
-#define FLASH_CYCLE2	0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i;
-	extern void flash_preinit(void);
-	extern void flash_afterinit(ulong);
-	ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
-	flash_preinit();
-
-	/* Init: no FLASHes known */
-	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		memset(&flash_info[i], 0, sizeof(flash_info_t));
-
-		flash_info[i].size =
-			flash_get_size((FPW *)flashbase, &flash_info[i]);
-
-		size += flash_info[i].size;
-		flashbase += 0x800000;
-	}
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
-	flash_afterinit(size);
-	return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-	FPWV *base = (FPWV *)(info->start[0]);
-
-	/* Put FLASH back in read mode */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
-	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-	int i;
-	flash_info_t * info;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-		info = & flash_info[i];
-		if (info->size &&
-			info->start[0] <= base && base <= info->start[0] + info->size - 1)
-			break;
-	}
-
-	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar *bootletter;
-	char *fmt;
-	uchar botbootletter[] = "B";
-	uchar topbootletter[] = "T";
-	uchar botboottype[] = "bottom boot sector";
-	uchar topboottype[] = "top boot sector";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	/* check for top or bottom boot, if it applies */
-	if (info->flash_id & FLASH_BTYPE) {
-		boottype = botboottype;
-		bootletter = botbootletter;
-	}
-	else {
-		boottype = topboottype;
-		bootletter = topbootletter;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMDLV065D:
-		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
-		break;
-	default:
-		fmt = "Unknown Chip Type\n";
-		break;
-	}
-
-	printf (fmt, bootletter, boottype);
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20,
-		info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-	int i;
-	FPWV* addr2;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
-	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
-
-	/* The manufacturer codes are only 1 byte, so just use 1 byte.
-	 * This works for any bus width and any FLASH device width.
-	 */
-	udelay(100);
-	switch (addr[0] & 0xff) {
-
-	case (uchar)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	case (uchar)INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
-	case (FPW)AMD_ID_LV065D:
-		info->flash_id += FLASH_AMDLV065D;
-		info->sector_count = 128;
-		info->size = 0x00800000;
-		for( i = 0; i < info->sector_count; i++ )
-			info->start[i] = (ulong)addr + (i * 0x10000);
-		break;				/* => 8 or 16 MB	*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* test for real flash at bank 1 */
-	addr2 = (FPW *)((ulong)addr | 0x800000);
-	if (addr2 != addr &&
-		((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
-		/* Seems 2 banks are the same space (8Mb chip is installed,
-		 * J24 in default position (CS0)). Disable this (first) bank.
-		 */
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-	}
-	/* Put FLASH back in read mode */
-	flash_reset(info);
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	FPWV *addr;
-	int flag, prot, sect;
-	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMDLV065D:
-		break;
-	case FLASH_UNKNOWN:
-	default:
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	last  = get_timer(0);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
-		if (info->protect[sect] != 0)	/* protected, skip it */
-			continue;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr = (FPWV *)(info->start[sect]);
-		if (intel) {
-			*addr = (FPW)0x00500050; /* clear status register */
-			*addr = (FPW)0x00200020; /* erase setup */
-			*addr = (FPW)0x00D000D0; /* erase confirm */
-		}
-		else {
-			/* must be AMD style if not Intel */
-			FPWV *base;		/* first address in bank */
-
-			base = (FPWV *)(info->start[0]);
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
-			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-			*addr = (FPW)0x00300030;	/* erase sector */
-		}
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		start = get_timer(0);
-
-		/* wait at least 50us for AMD, 80us for Intel.
-		 * Let's wait 1 ms.
-		 */
-		udelay (1000);
-
-		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-				printf ("Timeout\n");
-
-				if (intel) {
-					/* suspend erase	*/
-					*addr = (FPW)0x00B000B0;
-				}
-
-				flash_reset(info);	/* reset to read mode */
-				rcode = 1;		/* failed */
-				break;
-			}
-
-			/* show that we're waiting */
-			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
-				putc ('.');
-				last = get_timer(0);
-			}
-		}
-
-		/* show that we're waiting */
-		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
-			putc ('.');
-			last = get_timer(0);
-		}
-
-		flash_reset(info);	/* reset to read mode	*/
-	}
-
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-	int bytes;	  /* number of bytes to program in current word		*/
-	int left;	  /* number of bytes left to program			*/
-	int i, res;
-
-	for (left = cnt, res = 0;
-		 left > 0 && res == 0;
-		 addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-		bytes = addr & (sizeof(data) - 1);
-		addr &= ~(sizeof(data) - 1);
-
-		/* combine source and destination data so can program
-		 * an entire word of 16 or 32 bits
-		 */
-		for (i = 0; i < sizeof(data); i++) {
-			data <<= 8;
-			if (i < bytes || i - bytes >= left )
-				data += *((uchar *)addr + i);
-			else
-				data += *src++;
-		}
-
-		/* write one word to the flash */
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			res = write_word_amd(info, (FPWV *)addr, data);
-			break;
-		default:
-			/* unknown flash type, error! */
-			printf ("missing or unknown FLASH type\n");
-			res = 1;	/* not really a timeout, but gives error */
-			break;
-		}
-	}
-
-	return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-	ulong start;
-	int flag;
-	int res = 0;	/* result, assume success	*/
-	FPWV *base;		/* first address in flash bank	*/
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-
-	base = (FPWV *)(info->start[0]);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data	*/
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dest = (FPW)0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-
-	return (res);
-}
-#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
deleted file mode 100644
index f0af24ad9b..0000000000
--- a/board/icecube/icecube.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-
-#if defined(CONFIG_LITE5200B)
-#include "mt46v32m16.h"
-#else
-# if defined(CONFIG_MPC5200_DDR)
-#  include "mt46v16m16-75.h"
-# else
-#include "mt48lc16m16a2-75.h"
-# endif
-#endif
-
-#ifdef CONFIG_LITE5200B_PM
-/* u-boot part of low-power mode implementation */
-#define SAVED_ADDR (*(void **)0x00000000)
-#define PSC2_4 0x02
-
-void lite5200b_wakeup(void)
-{
-	unsigned char wakeup_pin;
-	void (*linux_wakeup)(void);
-
-	/* check PSC2_4, if it's down "QT" is signaling we have a wakeup
-	 * from low power mode */
-	*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
-	__asm__ volatile ("sync");
-
-	wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
-	if (wakeup_pin & PSC2_4)
-		return;
-
-	/* acknowledge to "QT"
-	 * by holding pin at 1 for 10 uS */
-	*(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
-	__asm__ volatile ("sync");
-	*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
-	__asm__ volatile ("sync");
-	udelay(10);
-
-	/* put ram out of self-refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000;	/* mode_en */
-	__asm__ volatile ("sync");
-	*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000;	/* cke ref_en */
-	__asm__ volatile ("sync");
-	*(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000;	/* !mode_en */
-	__asm__ volatile ("sync");
-	udelay(10); /* wait a bit */
-
-	/* jump back to linux kernel code */
-	linux_wakeup = SAVED_ADDR;
-	printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
-			(unsigned long)linux_wakeup);
-	linux_wakeup();
-}
-#else
-#define lite5200b_wakeup()
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	lite5200b_wakeup();
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-#if defined (CONFIG_LITE5200B)
-	puts ("Board: Freescale Lite5200B\n");
-#else
-	puts ("Board: Motorola MPC5200 (IceCube)\n");
-#endif
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x800000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
deleted file mode 100644
index 919876fd63..0000000000
--- a/board/icecube/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x705f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
deleted file mode 100644
index a200bc78e8..0000000000
--- a/board/icecube/mt46v32m16.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/icecube/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000