powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x

There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

102 files changed, 0 insertions, 11087 deletions

diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig
deleted file mode 100644
index 444c450d8a..0000000000
--- a/board/a3m071/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A3M071
-
-config SYS_BOARD
-	default "a3m071"
-
-config SYS_CONFIG_NAME
-	default "a3m071"
-
-endif
diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS
deleted file mode 100644
index 975107d2c0..0000000000
--- a/board/a3m071/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-A3M071 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/a3m071/
-F:	include/configs/a3m071.h
-F:	configs/a3m071_defconfig
-F:	configs/a4m2k_defconfig
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
deleted file mode 100644
index 4e31e33936..0000000000
--- a/board/a3m071/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a3m071.o
diff --git a/board/a3m071/README b/board/a3m071/README
deleted file mode 100644
index 112c47b60d..0000000000
--- a/board/a3m071/README
+++ /dev/null
@@ -1,80 +0,0 @@
-------------------------------------------------------------------------
-A3M071 board support
-------------------------------------------------------------------------
-
-
-SPL NOR flash support:
-----------------------
-To boot fast into the OS (Linux), this board port integrates the SPL
-framework. This means, that a special, stripped-down version of
-U-Boot runs in the beginning. In the case of the A3M071 board, this
-SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
-boot the OS (Linux) or a "real", full-blown U-Boot. This detection
-on whether to boot Linux or U-Boot is done by using the "boot_os"
-environment variable. If "boot_os" is set to "yes", Linux will be
-loaded and booted from the SPL U-Boot version. Otherwise, the
-full-blown U-Boot version will be loaded and run.
-
-Enabling Linux booting:
------------------------
-From U-Boot:
-=> setenv boot_os yes
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os yes
-
-Enabling U-Boot booting:
-------------------------
-From U-Boot:
-=> setenv boot_os no
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os no
-
-
-Preparing Linux image(s) for booting from SPL U-Boot:
------------------------------------------------------
-To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
-prepard/patched first. U-Boot usually inserts some dynamic values into
-the DT binary (blob), e.g. autodetected memory size, MAC addresses,
-clocks speeds etc. To generate this patched DT blob, you can use
-the following command:
-
-1. Load fdt blob to SDRAM:
-=> tftp 1800000 a3m071/a3m071.dtb
-
-2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
-=> run mtdargs addip2 addtty
-
-3. Use "fdt" commands to patch the DT blob:
-=> fdt addr 1800000
-=> fdt boardsetup
-=> fdt chosen
-
-4. Display patched DT blob (optional):
-=> fdt print
-
-5. Save fdt to NOR flash:
-=> erase fc180000 fc07ffff
-=> cp.b 1800000 fc180000 10000
-
-All this can be integrated into an environment command:
-=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
-	fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
-	cp.b 1800000 fc180000 10000'
-=> saveenv
-
-After this, only "run upd_fdt" needs to get called to load, patch
-and save the DT blob into NOR flash.
-
-Additionally, the Linux kernel image has to be saved uncompressed in
-its uImage file (and not gzip compressed). This can be done with this
-command:
-
-$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
-
-------------------------------------------------------------------------
-Stefan Roese, 2012-08-23
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
deleted file mode 100644
index 7e16aaf4b2..0000000000
--- a/board/a3m071/a3m071.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <miiphy.h>
-#include <linux/compiler.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_A4M2K
-#include "is46r16320d.h"
-#else
-#include "mt46v16m16-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-
-	/*
-	 * Wait a short while for the DLL to lock before accessing
-	 * the SDRAM
-	 */
-	udelay(100);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);	/* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-#ifdef SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0);	/* disabled */
-	}
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-static void get_revisions(int *failsavelevel, int *digiboardversion,
-	int *fpgaversion)
-{
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-	u8 val;
-
-	/* read digitalboard-version from TMR[2..4] */
-	val = 0;
-	val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
-	val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-	val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-	*digiboardversion = val;
-
-	/*
-	 * A4M2K only supports digiboardversion. No failsavelevel and
-	 * fpgaversion here.
-	 */
-#if !defined(CONFIG_A4M2K)
-	/*
-	 * Figure out failsavelevel
-	 * see ticket dsvk#59
-	 */
-	*failsavelevel = 0;	/* 0=failsave, 1=board ok, 2=fpga ok */
-
-	if (*digiboardversion == 0) {
-		*failsavelevel = 1;	/* digiboard-version ok */
-
-		/* read fpga-version from TMR[5..7] */
-		val = 0;
-		val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
-		val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-		val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-		*fpgaversion = val;
-
-		if (*fpgaversion == 1)
-			*failsavelevel = 2;	/* fpga-version ok */
-	}
-#endif
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_A4M2K)
-	/* enable CS3 and CS5 (FPGA) */
-	setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
-#else
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-	u32 val;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-	val = in_be32(&mm->ipbi_ws_ctrl);
-
-	/* first clear bits 19..21 (CS3...5) */
-	val &= ~((1 << 19) | (1 << 20) | (1 << 21));
-	if (failsavelevel == 2) {
-		/* FPGA ok */
-		val |= (1 << 19) | (1 << 21);
-	}
-
-	if (failsavelevel >= 1) {
-		/* at least digiboard-version ok */
-		val |= (1 << 20);
-	}
-
-	/* And write new value back to register */
-	out_be32(&mm->ipbi_ws_ctrl, val);
-
-
-	/* Setup pin multiplexing */
-	if (failsavelevel == 2) {
-		/* fpga-version ok */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
-#endif
-	} else if (failsavelevel == 1) {
-		/* digiboard-version ok - fpga not */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
-#endif
-	} else {
-		/* full failsave-mode */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
-#endif
-	}
-#endif
-
-	/*
-	 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
-	 * ticket #60
-	 *
-	 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
-	 * set bit 0(msb) to 1
-	 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
-
-#if defined(CONFIG_A4M2K)
-	/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
-
-	/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 15);
-	gpio->simple_ddr |= 1 << (31 - 14);
-	gpio->simple_ddr |= 1 << (31 - 13);
-	gpio->simple_ddr |= 1 << (31 - 12);
-
-	/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 15);
-	gpio->simple_gpioe |= 1 << (31 - 14);
-	gpio->simple_gpioe |= 1 << (31 - 13);
-	gpio->simple_gpioe |= 1 << (31 - 12);
-
-	/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
-
-	/* set PSC2[0..2] (STSLED[0..2]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 27);
-	gpio->simple_ddr |= 1 << (31 - 26);
-	gpio->simple_ddr |= 1 << (31 - 25);
-
-	/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 27);
-	gpio->simple_gpioe |= 1 << (31 - 26);
-	gpio->simple_gpioe |= 1 << (31 - 25);
-
-	/* Setup PSC6[2] as MRST2 self reset GPIO output */
-
-	/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
-	gpio->simple_ode |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
-	gpio->simple_dvo |= 1 << (31 - 3);
-
-	/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 3);
-
-	/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
-
-	/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
-	gpio->simple_ddr |= 0 << (31 - 2);
-
-	/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 2);
-#else
-	/* setup GPIOs for status-leds if needed - see ticket #57 */
-	if (failsavelevel > 0) {
-		/* digiboard-version is OK */
-		/* LED is LOW ACTIVE - so deactivate by set output to 1 */
-		gpio->simple_dvo |= 1 << (31 - 12);
-		gpio->simple_dvo |= 1 << (31 - 13);
-		/* set GPIO direction to output */
-		gpio->simple_ddr |= 1 << (31 - 12);
-		gpio->simple_ddr |= 1 << (31 - 13);
-		/* open drain config is set to "normal output" at reset */
-		/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
-		/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
-		/* enable as GPIO */
-		gpio->simple_gpioe |= 1 << (31 - 12);
-		gpio->simple_gpioe |= 1 << (31 - 13);
-	}
-
-	/* setup fpga irq - see ticket #65 */
-	if (failsavelevel > 1) {
-		/*
-		 * The main irq initialisation is done in interrupts.c
-		 * mpc5xxx_init_irq
-		 */
-		struct mpc5xxx_intr *intr =
-		    (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
-
-		setbits_be32(&intr->ctrl, 0x08C01801);
-
-		/*
-		 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
-		 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
-		 */
-	}
-#endif
-}
-
-int checkboard(void)
-{
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-#ifdef CONFIG_A4M2K
-	puts("Board: A4M2K\n");
-	printf("       digiboard IO version %u\n", digiboardversion);
-#else
-	puts("Board: A3M071\n");
-	printf("Rev:   failsave level       %u\n", failsavelevel);
-	printf("       digiboard IO version %u\n", digiboardversion);
-	if (failsavelevel > 0)	/* only if fpga-version red */
-		printf("       fpga IO version      %u\n", fpgaversion);
-#endif
-
-	return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	/* adjust flash start and offset to detected values */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	gd->bd->bi_flashoffset = 0;
-
-	/* adjust mapping */
-	out_be32((void *)MPC5XXX_BOOTCS_START,
-		 START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_BOOTCS_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-	out_be32((void *)MPC5XXX_CS0_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * A3M071 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
-			    *s == 't' || *s == 'T'))
-		return 0;
-
-	return 1;
-}
-#endif
-
-#if defined(CONFIG_HW_WATCHDOG)
-static int watchdog_toggle;
-
-void hw_watchdog_reset(void)
-{
-	int val;
-
-	/*
-	 * Check if watchdog is enabled via user command
-	 */
-	if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
-		/* Set direction to output */
-		setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
-
-		/*
-		 * Toggle watchdog output
-		 */
-		val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-		       CONFIG_WDOG_GPIO_PIN);
-		if (val) {
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		} else {
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		}
-	}
-}
-
-int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 2)
-		goto usage;
-
-	if (strncmp(argv[1], "on", 2) == 0)
-		watchdog_toggle = 1;
-	else if (strncmp(argv[1], "off", 3) == 0)
-		watchdog_toggle = 0;
-	else
-		goto usage;
-
-	return 0;
-usage:
-	printf("Usage: wdogtoggle %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
-	"toggle GPIO pin to service watchdog",
-	"[on/off] - Switch watchdog toggling via GPIO pin on/off"
-);
-#endif
diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h
deleted file mode 100644
index 981359f22b..0000000000
--- a/board/a3m071/is46r16320d.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
-
-/* SDRAM Config Standard timing */
-#define SDRAM_MODE	0x008d0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x70430f00
-#define SDRAM_CONFIG1	0x33622930
-#define SDRAM_CONFIG2	0x46670000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
deleted file mode 100644
index 8f428306fe..0000000000
--- a/board/a3m071/mt46v16m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig
deleted file mode 100644
index ba5447fb9a..0000000000
--- a/board/a4m072/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A4M072
-
-config SYS_BOARD
-	default "a4m072"
-
-config SYS_CONFIG_NAME
-	default "a4m072"
-
-endif
diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS
deleted file mode 100644
index 83dc59e87f..0000000000
--- a/board/a4m072/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-A4M072 BOARD
-M:	Sergei Poselenov <sposelenov@emcraft.com>
-S:	Maintained
-F:	board/a4m072/
-F:	include/configs/a4m072.h
-F:	configs/a4m072_defconfig
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
deleted file mode 100644
index 2a40e5799e..0000000000
--- a/board/a4m072/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a4m072.o
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
deleted file mode 100644
index 6f0d4489a2..0000000000
--- a/board/a4m072/a4m072.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <netdev.h>
-#include <led-display.h>
-#include <linux/err.h>
-
-#include "mt46v32m16.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: A4M072\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize FEC.\n");
-
-	if ((rv = pci_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * Initialize EEPROM write-protect GPIO pin.
- */
-int misc_init_r(void)
-{
-#if defined(CONFIG_SYS_EEPROM_WREN)
-	/* Enable GPIO pin */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
-	/* Set direction, output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
-	/* De-assert write enable */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-#endif
-	return 0;
-}
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
- *	               0: disable write
- *		       1: enable write
- *  Returns:           -1: wrong device address
- *                      0: dis-/en- able done
- *		     0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access */
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access */
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-						   CONFIG_SYS_EEPROM_WP));
-			break;
-		}
-	}
-	return state;
-}
-#endif
-
-#ifdef CONFIG_CMD_DISPLAY
-#define DISPLAY_BUF_SIZE	2
-static u8 display_buf[DISPLAY_BUF_SIZE];
-static u8 display_putc_pos;
-static u8 display_out_pos;
-
-void display_set(int cmd) {
-
-	if (cmd & DISPLAY_CLEAR) {
-		display_buf[0] = display_buf[1] = 0;
-	}
-
-	if (cmd & DISPLAY_HOME) {
-		display_putc_pos = 0;
-	}
-}
-
-#define SEG_A    (1<<0)
-#define SEG_B    (1<<1)
-#define SEG_C    (1<<2)
-#define SEG_D    (1<<3)
-#define SEG_E    (1<<4)
-#define SEG_F    (1<<5)
-#define SEG_G    (1<<6)
-#define SEG_P    (1<<7)
-#define SEG__    0
-
-/*
- * +- A -+
- * |     |
- * F     B
- * |     |
- * +- G -+
- * |     |
- * E     C
- * |     |
- * +- D -+  P
- *
- * 0..9		index 0..9
- * A..Z		index 10..35
- * -		index 36
- * _		index 37
- * .		index 38
- */
-
-#define SYMBOL_DASH		(36)
-#define SYMBOL_UNDERLINE	(37)
-#define SYMBOL_DOT		(38)
-
-static u8 display_char2seg7_tbl[]=
-{
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
-	SEG_B | SEG_C,						/* 1 */
-	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
-	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
-	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
-	SEG_A | SEG_B | SEG_C,					/* 7 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
-	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
-	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
-	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
-	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
-	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
-	0,					/* g - not displayed */
-	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
-	SEG_B | SEG_C,						/* I */
-	0,					/* J - not displayed */
-	0,					/* K - not displayed */
-	SEG_D | SEG_E | SEG_F,					/* L */
-	0,					/* m - not displayed */
-	0,					/* n - not displayed */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
-	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
-	0,					/* q - not displayed */
-	0,					/* r - not displayed */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
-	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
-	0,					/* V - not displayed */
-	0,					/* w - not displayed */
-	0,					/* X - not displayed */
-	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
-	0,					/* Z - not displayed */
-	SEG_G,							/* - */
-	SEG_D,							/* _ */
-	SEG_P							/* . */
-};
-
-/* Convert char to the LED segments representation */
-static u8 display_char2seg7(char c)
-{
-	u8 val = 0;
-
-	if (c >= '0' && c <= '9')
-		c -= '0';
-	else if (c >= 'a' && c <= 'z')
-		c -= 'a' - 10;
-	else if (c >= 'A' && c <= 'Z')
-		c -= 'A' - 10;
-	else if (c == '-')
-		c = SYMBOL_DASH;
-	else if (c == '_')
-		c = SYMBOL_UNDERLINE;
-	else if (c == '.')
-		c = SYMBOL_DOT;
-	else
-		c = ' ';	/* display unsupported symbols as space */
-
-	if (c != ' ')
-		val = display_char2seg7_tbl[(int)c];
-
-	return val;
-}
-
-int display_putc(char c)
-{
-	if (display_putc_pos >= DISPLAY_BUF_SIZE)
-		return -1;
-
-	display_buf[display_putc_pos++] = display_char2seg7(c);
-	/* one-symbol message should be steady */
-	if (display_putc_pos == 1)
-		display_buf[display_putc_pos] = display_char2seg7(c);
-
-	return c;
-}
-
-/*
- * Flush current symbol to the LED display hardware
- */
-static inline void display_flush(void)
-{
-	u32 val = display_buf[display_out_pos];
-
-	val |= (val << 8) | (val << 16) | (val << 24);
-	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
-}
-
-/*
- * Output contents of the software display buffer to the LED display every 0.5s
- */
-void board_show_activity(ulong timestamp)
-{
-	static ulong last;
-	static u8 once;
-
-	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
-		display_flush();
-		display_out_pos ^= 1;
-		last = timestamp;
-		once = 1;
-	}
-}
-
-/*
- * Empty fake function
- */
-void show_activity(int arg)
-{
-}
-#endif
-#if defined (CONFIG_SHOW_BOOT_PROGRESS)
-static int a4m072_status2code(int status, char *buf)
-{
-	char c = 0;
-
-	if (((status > 0) && (status <= 8)) ||
-				((status >= 100) && (status <= 108)) ||
-				((status < 0) && (status >= -9)) ||
-				(status == -100) || (status == -101) ||
-				((status <= -103) && (status >= -113))) {
-		c = '5';
-	} else if (((status >= 9) && (status <= 14)) ||
-			((status >= 120) && (status <= 123)) ||
-			((status >= 125) && (status <= 129)) ||
-			((status >= -13) && (status <= -10)) ||
-			(status == -120) || (status == -122) ||
-			((status <= -124) && (status >= -127)) ||
-			(status == -129)) {
-		c = '8';
-	} else if (status == 15) {
-		c = '9';
-	} else if ((status <= -30) && (status >= -32)) {
-		c = 'A';
-	} else if (((status <= -35) && (status >= -40)) ||
-			((status <= -42) && (status >= -51)) ||
-			((status <= -53) && (status >= -58)) ||
-			(status == -64) ||
-			((status <= -80) && (status >= -83)) ||
-			(status == -130) || (status == -140) ||
-			(status == -150)) {
-		c = 'B';
-	}
-
-	if (c == 0)
-		return -EINVAL;
-
-	buf[0] = (status < 0) ? '-' : c;
-	buf[1] = c;
-
-	return 0;
-}
-
-void show_boot_progress(int status)
-{
-	char buf[2];
-
-	if (a4m072_status2code(status, buf) < 0)
-		return;
-
-	display_putc(buf[0]);
-	display_putc(buf[1]);
-	display_set(DISPLAY_HOME);
-	display_out_pos = 0;	/* reset output position */
-
-	/* we want to flush status 15 now */
-	if (status == BOOTSTAGE_ID_RUN_OS)
-		display_flush();
-}
-#endif
diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h
deleted file mode 100644
index c0a08a8452..0000000000
--- a/board/a4m072/mt46v32m16.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig
deleted file mode 100644
index b5cf2057f4..0000000000
--- a/board/canmb/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CANMB
-
-config SYS_BOARD
-	default "canmb"
-
-config SYS_CONFIG_NAME
-	default "canmb"
-
-endif
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
deleted file mode 100644
index 71750ead47..0000000000
--- a/board/canmb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CANMB BOARD
-#M:	-
-S:	Maintained
-F:	board/canmb/
-F:	include/configs/canmb.h
-F:	configs/canmb_defconfig
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
deleted file mode 100644
index 4286a9123c..0000000000
--- a/board/canmb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= canmb.o
-
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
deleted file mode 100644
index 54de0e2673..0000000000
--- a/board/canmb/canmb.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m32s2-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: CANMB\n");
-	return 0;
-}
-
-int board_early_init_r (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
-	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
-	return 0;
-}
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/canmb/mt48lc16m32s2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig
deleted file mode 100644
index ccea5c96e4..0000000000
--- a/board/cm5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM5200
-
-config SYS_BOARD
-	default "cm5200"
-
-config SYS_CONFIG_NAME
-	default "cm5200"
-
-endif
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
deleted file mode 100644
index 1e1df3f6dc..0000000000
--- a/board/cm5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/cm5200/
-F:	include/configs/cm5200.h
-F:	configs/cm5200_defconfig
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
deleted file mode 100644
index 76f8b9fc05..0000000000
--- a/board/cm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
deleted file mode 100644
index 0c647bbd3d..0000000000
--- a/board/cm5200/cm5200.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * Adapted to U-Boot 1.2 by:
- *   Bartlomiej Sieka <tur@semihalf.com>:
- *      - HW ID readout from EEPROM
- *      - module detection
- *   Grzegorz Bernacki <gjb@semihalf.com>:
- *      - run-time SDRAM controller configuration
- *      - LIBFDT support
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-
-#include "cm5200.h"
-#include "fwupdate.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static hw_id_t hw_id;
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Retrieve memory configuration for a given module. board_type is the index
- * in hw_id_list[] corresponding to the module we are executing on; we return
- * SDRAM controller settings approprate for this module.
- */
-static mem_conf_t* get_mem_config(int board_type)
-{
-	switch(board_type){
-		case CM1_QA:
-			return memory_config[0];
-		case CM11_QA:
-		case CMU1_QA:
-			return memory_config[1];
-		default:
-			printf("ERROR: Unknown module, using a default SDRAM "
-				"configuration - things may not work!!!.\n");
-			return memory_config[0];
-	}
-}
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-	mem_conf_t *mem_conf;
-
-	mem_conf = get_mem_config(gd->board_type);
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
-
-	sdram_start(0, mem_conf);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1, mem_conf);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0, mem_conf);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller.  Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
-	 * the MPC5200B User's Manual.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-	__asm__ volatile ("sync");
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-
-/*
- * Read module hardware identification data from the I2C EEPROM.
- */
-static void read_hw_id(hw_id_t hw_id)
-{
-	printf("ERROR: can't read HW ID from EEPROM\n");
-}
-
-
-/*
- * Identify module we are running on, set gd->board_type to the index in
- * hw_id_list[] corresponding to the module identifed, or to
- * CM5200_UNKNOWN_MODULE if we can't identify the module.
- */
-static void identify_module(hw_id_t hw_id)
-{
-	int i, j, element;
-	char match;
-	gd->board_type = CM5200_UNKNOWN_MODULE;
-	for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
-		match = 1;
-		for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
-			element = hw_id_identify[j];
-			if (strncmp(hw_id_list[i][element],
-					&hw_id[element][0],
-					hw_id_format[element].length) != 0) {
-				match = 0;
-				break;
-			}
-		}
-		if (match) {
-			gd->board_type = i;
-			break;
-		}
-	}
-}
-
-
-/*
- * Compose string with module name.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_module_name(hw_id_t hw_id, char *buf)
-{
-	char tmp[MODULE_NAME_MAXLEN];
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, ".", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	strncat(buf, " (", 2);
-	strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
-		hw_id_format[IDENTIFICATION_NUMBER].length);
-	sprintf(tmp, " / %u.%u)",
-		hw_id[MAJOR_SW_VERSION][0],
-		hw_id[MINOR_SW_VERSION][0]);
-	strcat(buf, tmp);
-}
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-/*
- * Compose string with hostname.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_hostname(hw_id_t hw_id, char *buf)
-{
-	char *p;
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, "_", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	for (p = buf; *p; ++p)
-		*p = tolower(*p);
-
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/*
- * Update 'model' and 'memory' properties in the blob according to the module
- * that we are running on.
- */
-static void ft_blob_update(void *blob, bd_t *bd)
-{
-	int len, ret, nodeoffset = 0;
-	char module_name[MODULE_NAME_MAXLEN] = {0};
-
-	compose_module_name(hw_id, module_name);
-	len = strlen(module_name) + 1;
-
-	ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
-	if (ret < 0)
-	printf("ft_blob_update(): cannot set /model property err:%s\n",
-		fdt_strerror(ret));
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-/*
- * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
- * that we need to use local variable for readout, because global data is not
- * writable yet (and we'll have to redo the readout later on).
- */
-int checkboard(void)
-{
-	hw_id_t hw_id_tmp;
-	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
-
-	read_hw_id(hw_id_tmp);
-	identify_module(hw_id_tmp);	/* this sets gd->board_type */
-	compose_module_name(hw_id_tmp, module_name_tmp);
-
-	if (gd->board_type != CM5200_UNKNOWN_MODULE)
-		printf("Board: %s\n", module_name_tmp);
-	else
-		printf("Board: unrecognized cm5200 module (%s)\n",
-			module_name_tmp);
-
-	return 0;
-}
-
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/* Now that we can write to global data, read HW ID again. */
-	read_hw_id(hw_id);
-	return 0;
-}
-
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#if defined(CONFIG_SYS_I2C_SOFT)
-	uchar buf[6];
-	char str[18];
-	char hostname[MODULE_NAME_MAXLEN];
-
-	/* Read ethaddr from EEPROM */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
-		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
-			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
-		/* Check if MAC addr is owned by Schindler */
-		if (strstr(str, "00:06:C3") != str)
-			printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
-				" in EEPROM.\n", str);
-		else {
-			printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
-				str);
-			setenv("ethaddr", str);
-		}
-	} else {
-		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
-			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
-			CONFIG_MAC_OFFSET);
-	}
-	hostname[0] = 0x00;
-	/* set the hostname appropriate to the module we're running on */
-	compose_hostname(hw_id, hostname);
-	setenv("hostname", hostname);
-
-#endif /* defined(CONFIG_SYS_I2C_SOFT) */
-	if (!getenv("ethaddr"))
-		printf(LOG_PREFIX "MAC address not set, networking is not "
-					"operational\n");
-
-	return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-
-#ifdef CONFIG_LAST_STAGE_INIT
-int last_stage_init(void)
-{
-#ifdef CONFIG_USB_STORAGE
-	cm5200_fwupdate();
-#endif /* CONFIG_USB_STORAGE */
-	return 0;
-}
-#endif /* CONFIG_LAST_STAGE_INIT */
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_blob_update(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h
deleted file mode 100644
index c2573f3bf6..0000000000
--- a/board/cm5200/cm5200.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Bartlomiej Sieka <tur@semihalf.com>
- * Author: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CM5200_H
-#define _CM5200_H
-
-
-/*
- * Definitions and declarations for the modules of the cm5200 platform. Mostly
- * related to reading the hardware identification data (HW ID) from the I2C
- * EEPROM, detection of the particular module we are executing on, and
- * appropriate SDRAM controller initialization.
- */
-
-
-#define CM5200_UNKNOWN_MODULE	0xffffffff
-
-enum {
-	DEVICE_NAME,		/* 0 */
-	GENERATION,		/* 1 */
-	PCB_NAME,		/* 2 */
-	FORM,			/* 3 */
-	VERSION,		/* 4 */
-	IDENTIFICATION_NUMBER,	/* 5 */
-	MAJOR_SW_VERSION,	/* 6 */
-	MINOR_SW_VERSION,	/* 7 */
-	/* add new alements above this line */
-	HW_ID_ELEM_COUNT	/* count */
-};
-
-/*
- * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
- */
-
-#define DEVICE_NAME_OFFSET		0x02
-#define GENERATION_OFFSET		0x0b
-#define PCB_NAME_OFFSET			0x0c
-#define FORM_OFFSET			0x15
-#define VERSION_OFFSET			0x16
-#define IDENTIFICATION_NUMBER_OFFSET	0x19
-#define MAJOR_SW_VERSION_OFFSET		0x0480
-#define MINOR_SW_VERSION_OFFSET		0x0481
-
-
-#define DEVICE_NAME_LEN			0x09
-#define GENERATION_LEN			0x01
-#define PCB_NAME_LEN			0x09
-#define FORM_LEN			0x01
-#define VERSION_LEN			0x03
-#define IDENTIFICATION_NUMBER_LEN	0x09
-#define MAJOR_SW_VERSION_LEN		0x01
-#define MINOR_SW_VERSION_LEN		0x01
-
-#define HW_ID_ELEM_MAXLEN		0x09	/* MAX(XXX_LEN) */
-
-/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
-#define MODULE_NAME_MAXLEN		64
-
-
-/* storage for HW ID read from EEPROM */
-typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
-
-
-/* HW ID layout in EEPROM */
-static struct {
-	unsigned int offset;
-	unsigned int length;
-} hw_id_format[HW_ID_ELEM_COUNT] = {
-	{DEVICE_NAME_OFFSET,		DEVICE_NAME_LEN},
-	{GENERATION_OFFSET,		GENERATION_LEN},
-	{PCB_NAME_OFFSET,		PCB_NAME_LEN},
-	{FORM_OFFSET,			FORM_LEN},
-	{VERSION_OFFSET,		VERSION_LEN},
-	{IDENTIFICATION_NUMBER_OFFSET,	IDENTIFICATION_NUMBER_LEN},
-	{MAJOR_SW_VERSION_OFFSET,	MAJOR_SW_VERSION_LEN},
-	{MINOR_SW_VERSION_OFFSET,	MINOR_SW_VERSION_LEN},
-};
-
-
-/* HW ID data found in EEPROM on supported modules */
-static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"591881",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM11",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594200",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CMU",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CMU1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594128",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-
-/* list of known modules */
-static char **hw_id_list[] = {
-	cm1_qa_hw_id,
-	cm11_qa_hw_id,
-	cmu1_qa_hw_id,
-};
-
-/* indices to the above list - keep in sync */
-enum {
-	CM1_QA,
-	CM11_QA,
-	CMU1_QA,
-};
-
-
-/* identify modules based on these hw id elements */
-static int hw_id_identify[] = {
-	PCB_NAME,
-	FORM,
-	VERSION,
-};
-
-
-/* Registers' settings for SDRAM controller intialization */
-typedef struct {
-	ulong mode;
-	ulong control;
-	ulong config1;
-	ulong config2;
-} mem_conf_t;
-
-static mem_conf_t k4s561632E = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xE2333900,
-	0x8EE70000
-};
-
-static mem_conf_t mt48lc32m16a2 = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xD2322800,
-	0x8AD70000
-};
-
-static mem_conf_t* memory_config[] = {
-	&k4s561632E,
-	&mt48lc32m16a2
-};
-
-#endif /* _CM5200_H */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
deleted file mode 100644
index 60097dc8c7..0000000000
--- a/board/cm5200/cmd_cm5200.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
- *
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <usb.h>
-
-#ifdef CONFIG_CMD_BSP
-
-static int do_usb_test(char * const argv[])
-{
-	int i;
-	static int usb_stor_curr_dev = -1; /* current device */
-
-	printf("Starting USB Test\n"
-		"Please insert USB Memmory Stick\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	usb_stop();
-	printf("(Re)start USB...\n");
-	i = usb_init();
-#ifdef CONFIG_USB_STORAGE
-		/* try to recognize storage devices immediately */
-		if (i >= 0)
-			usb_stor_curr_dev = usb_stor_scan(1);
-#endif /* CONFIG_USB_STORAGE */
-	if (usb_stor_curr_dev >= 0)
-		printf("Found USB Storage Dev continue with Test...\n");
-	else {
-		printf("No USB Storage Device detected.. Stop Test\n");
-		return 1;
-	}
-
-	usb_stor_info();
-
-	printf("stopping USB..\n");
-	usb_stop();
-
-	return 0;
-}
-
-static int do_led_test(char * const argv[])
-{
-	int i = 0;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	printf("Starting LED Test\n"
-		"Please set Switch S500 all off\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	/* configure timer 2-3 for simple GPIO output High */
-	gpt->gpt2.emsr |= 0x00000034;
-	gpt->gpt3.emsr |= 0x00000034;
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
-	(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
-	printf("Please press any key to stop\n\n");
-	while (!tstc()) {
-		if (i == 1) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr &= ~0x00000010;
-		} else if (i == 2) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr |= 0x00000010;
-		} else if (i >= 3) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt3.emsr &= ~0x00000010;
-			gpt->gpt2.emsr |= 0x00000010;
-			i = 0;
-		}
-		i++;
-		udelay(200000);
-	}
-	getc();
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-	gpt->gpt2.emsr |= 0x00000010;
-	gpt->gpt3.emsr |= 0x00000010;
-
-	return 0;
-}
-
-static int do_rs232_test(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	/* Configure PSC 2-3-6 as GPIO */
-	gpio->port_config &= 0xFF0FF80F;
-
-	switch (simple_strtoul(argv[2], NULL, 10)) {
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		printf("Uart 1 test: RX TX tested by using U-Boot\n"
-			"Please connect RTS with CTS on Uart1 plug\n\n"
-			"Press any key to start\n\n");
-		getc();
-
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-		break;
-	case 2:
-		/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
-		printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x000000F0);
-		gpio->simple_gpioe |= 0x000000F0;
-		gpio->simple_ddr &= ~(0x000000F0);
-		gpio->simple_ddr |= 0x00000050;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-		break;
-	case 3:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x00000F00);
-		gpio->simple_gpioe |= 0x00000F00;
-
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |= 0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-		break;
-	case 4:
-		/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
-		printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0xF0000000);
-		gpio->simple_gpioe |= 0x30000000;
-
-		gpio->simple_ddr &= ~(0xf0000000);
-		gpio->simple_ddr |= 0x30000000;
-
-		(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
-		(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x10000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x20000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-		break;
-	default:
-		printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
-
-	return error_status;
-}
-
-static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode = -1;
-
-	switch (argc) {
-	case 2:
-		if (strncmp(argv[1], "led", 3) == 0)
-			rcode = do_led_test(argv);
-		else if (strncmp(argv[1], "usb", 3) == 0)
-			rcode = do_usb_test(argv);
-		break;
-	case 3:
-		if (strncmp(argv[1], "rs232", 3) == 0)
-			rcode = do_rs232_test(argv);
-		break;
-	}
-
-	switch (rcode) {
-	case -1:
-		printf("Usage:\n"
-			"fkt { i2c | led | usb }\n"
-			"fkt rs232 number\n");
-		rcode = 1;
-		break;
-	case 0:
-		printf("Test passed\n");
-		break;
-	default:
-		printf("Test failed with code: %d\n", rcode);
-	}
-
-	return rcode;
-}
-
-U_BOOT_CMD(
-	fkt,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"i2c\n"
-	"     - Test I2C communication\n"
-	"fkt led\n"
-	"     - Test LEDs\n"
-	"fkt rs232 number\n"
-	"     - Test RS232 (loopback plug(s) for RS232 required)\n"
-	"fkt usb\n"
-	"     - Test USB communication"
-);
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
deleted file mode 100644
index 4740c8394c..0000000000
--- a/board/cm5200/fwupdate.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Michel Marti <mma@objectxp.com>
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
- *   - code clean-up
- *   - bugfix for overwriting bootargs by user
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <fat.h>
-#include <malloc.h>
-#include <image.h>
-#include <usb.h>
-#include <fat.h>
-
-#include "fwupdate.h"
-
-static int load_rescue_image(ulong);
-
-void cm5200_fwupdate(void)
-{
-	cmd_tbl_t *bcmd;
-	char *rsargs;
-	char *tmp = NULL;
-	char ka[16];
-	char * const argv[3] = { "bootm", ka, NULL };
-
-	/* Check if rescue system is disabled... */
-	if (getenv("norescue")) {
-		printf(LOG_PREFIX "Rescue System disabled.\n");
-		return;
-	}
-
-	/* Check if we have a USB storage device and load image */
-	if (load_rescue_image(LOAD_ADDR))
-		return;
-
-	bcmd = find_cmd("bootm");
-	if (!bcmd)
-		return;
-
-	sprintf(ka, "%lx", (ulong)LOAD_ADDR);
-
-	/* prepare our bootargs */
-	rsargs = getenv("rs-args");
-	if (!rsargs)
-		rsargs = RS_BOOTARGS;
-	else {
-		tmp = malloc(strlen(rsargs+1));
-		if (!tmp) {
-			printf(LOG_PREFIX "Memory allocation failed\n");
-			return;
-		}
-		strcpy(tmp, rsargs);
-		rsargs = tmp;
-	}
-
-	setenv("bootargs", rsargs);
-
-	if (rsargs == tmp)
-		free(rsargs);
-
-	printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
-	do_bootm(bcmd, 0, 2, argv);
-}
-
-static int load_rescue_image(ulong addr)
-{
-	disk_partition_t info;
-	int devno;
-	int partno;
-	int i;
-	char fwdir[64];
-	char nxri[128];
-	char *tmp;
-	char dev[7];
-	char addr_str[16];
-	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
-	struct blk_desc *stor_dev = NULL;
-	cmd_tbl_t *bcmd;
-
-	/* Get name of firmware directory */
-	tmp = getenv("fw-dir");
-
-	/* Copy it into fwdir */
-	strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
-	fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
-
-	printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
-		" storage...\n", fwdir);
-	usb_stop();
-	if (usb_init() != 0)
-		return 1;
-
-	/* Check for storage device */
-	if (usb_stor_scan(1) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect storage device */
-	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
-		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
-		if (stor_dev->type != DEV_TYPE_UNKNOWN)
-			break;
-	}
-	if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
-		printf(LOG_PREFIX "No valid storage device found...\n");
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect partition */
-	for (partno = -1, i = 0; i < 6; i++) {
-		if (part_get_info(stor_dev, i, &info) == 0) {
-			if (fat_register_device(stor_dev, i) == 0) {
-				/* Check if rescue image is present */
-				FW_DEBUG("Looking for firmware directory '%s'"
-					" on partition %d\n", fwdir, i);
-				if (!fat_exists(fwdir)) {
-					FW_DEBUG("No NX rescue image on "
-						"partition %d.\n", i);
-					partno = -2;
-				} else {
-					partno = i;
-					FW_DEBUG("Partition %d contains "
-						"firmware directory\n", partno);
-					break;
-				}
-			}
-		}
-	}
-
-	if (partno < 0) {
-		switch (partno) {
-		case -1:
-			printf(LOG_PREFIX "Error: No valid (FAT) partition "
-				"detected\n");
-			break;
-		case -2:
-			printf(LOG_PREFIX "Error: No NX rescue image on FAT "
-				"partition\n");
-			break;
-		default:
-			printf(LOG_PREFIX "Error: Failed with code %d\n",
-				partno);
-		}
-		usb_stop();
-		return 1;
-	}
-
-	/* Load the rescue image */
-	bcmd = find_cmd("fatload");
-	if (!bcmd) {
-		printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
-		usb_stop();
-		return 1;
-	}
-
-	tmp = getenv("nx-rescue-image");
-	sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
-	sprintf(dev, "%d:%d", devno, partno);
-	sprintf(addr_str, "%lx", addr);
-
-	FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
-		dev, addr_str, nxri);
-
-	if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Stop USB */
-	usb_stop();
-	return 0;
-}
diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h
deleted file mode 100644
index 6ddf0bac35..0000000000
--- a/board/cm5200/fwupdate.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- *
- * Author: Michel Marti <mma@objectxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FW_UPDATE_H
-#define __FW_UPDATE_H
-
-/* Default prefix for output messages */
-#define LOG_PREFIX	"CM5200:"
-
-/* Extra debug macro */
-#ifdef CONFIG_FWUPDATE_DEBUG
-#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
-#else
-#define FW_DEBUG(fmt...)
-#endif
-
-/* Name of the directory holding firmware images */
-#define FW_DIR		"nx-fw"
-#define RESCUE_IMAGE	"nxrs.img"
-#define LOAD_ADDR	0x400000
-#define RS_BOOTARGS	"ramdisk_size=8192K"
-
-/* Main function for fwupdate */
-void cm5200_fwupdate(void);
-
-#endif /* __FW_UPDATE_H */
diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig
deleted file mode 100644
index 54a86b9e13..0000000000
--- a/board/davedenx/aria/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ARIA
-
-config SYS_BOARD
-	default "aria"
-
-config SYS_VENDOR
-	default "davedenx"
-
-config SYS_CONFIG_NAME
-	default "aria"
-
-endif
diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS
deleted file mode 100644
index a6152c985a..0000000000
--- a/board/davedenx/aria/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ARIA BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/davedenx/aria/
-F:	include/configs/aria.h
-F:	configs/aria_defconfig
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
deleted file mode 100644
index dd38b7f389..0000000000
--- a/board/davedenx/aria/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= aria.o
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
deleted file mode 100644
index e389819e9d..0000000000
--- a/board/davedenx/aria/aria.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	gd->ram_size = fixed_sdram(NULL, NULL, 0);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 tmp;
-
-	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
-	printf("FPGA:  %u-%u.%u.%u\n",
-		(tmp & 0xFF000000) >> 24,
-		(tmp & 0x00FF0000) >> 16,
-		(tmp & 0x0000FF00) >>  8,
-		 tmp & 0x000000FF
-	);
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/*
-	 * FEC
-	 */
-
-	/* FEC on PSCx_x*/
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-
-	/*
-	 * DIU
-	 */
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/*
-	 * On board SRAM
-	 */
-	/* FUNC2=/LPC CS6 */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-};
-
-int checkboard (void)
-{
-	puts("Board: ARIA\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig
deleted file mode 100644
index 3f2a411196..0000000000
--- a/board/esd/mecp5123/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5123
-
-config SYS_BOARD
-	default "mecp5123"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "mecp5123"
-
-endif
diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS
deleted file mode 100644
index ae5fcead90..0000000000
--- a/board/esd/mecp5123/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5123 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/mecp5123/
-F:	include/configs/mecp5123.h
-F:	configs/mecp5123_defconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
deleted file mode 100644
index f5ebb0144f..0000000000
--- a/board/esd/mecp5123/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mecp5123.o
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
deleted file mode 100644
index 78a6b66110..0000000000
--- a/board/esd/mecp5123/mecp5123.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	return -ENOSYS;
-}
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	int i;
-
-	/*
-	 * Initialize Local Window for boot access
-	 */
-	out_be32(&im->sysconf.lpbaw,
-		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
-	sync_law(&im->sysconf.lpbaw);
-
-	/*
-	 * Configure MSCAN clocks
-	 */
-	for (i=0; i<4; ++i) {
-		out_be32(&im->clk.msccr[i], 0x00300000);
-		out_be32(&im->clk.msccr[i], 0x00310000);
-	}
-
-	/*
-	 * Configure GPIO's
-	 */
-	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
-	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
-	setbits_be32(&im->gpio.gpdir, 0x001000e0);
-	setbits_be32(&im->gpio.gpdat, 0x00100000);
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 val;
-
-	/*
-	 * Optimize access to profibus chip (VPC3) on the local bus
-	 */
-
-	/*
-	 * Select 1:1 for LPC_DIV
-	 */
-	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
-	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
-
-	/*
-	 * Configure LPC Chips Select Deadcycle Control Register
-	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
-	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
-
-	/*
-	 * Configure LPC Chips Select Holdcycle Control Register
-	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
-	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
-
-	return 0;
-}
-
-static iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SELECT LPC_CS1 */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC7_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC9_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC11_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC0=SELECT IRQ0 */
-	{
-		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr;
-
-	puts("Board: MECP_5123\n");
-
-	/*
-	 * Initialize function mux & slew rate IO inter alia on IO
-	 * Pins
-	 */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	spridr = in_be32(&im->sysconf.spridr);
-	if (SVR_MJREV(spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig
deleted file mode 100644
index f125f9e596..0000000000
--- a/board/freescale/mpc5121ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC5121ADS
-
-config SYS_BOARD
-	default "mpc5121ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "mpc5121ads"
-
-endif
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
deleted file mode 100644
index d4aab8fb51..0000000000
--- a/board/freescale/mpc5121ads/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC5121ADS BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc5121ads/
-F:	include/configs/mpc5121ads.h
-F:	configs/mpc5121ads_defconfig
-F:	configs/mpc5121ads_rev2_defconfig
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
deleted file mode 100644
index 67cf55546b..0000000000
--- a/board/freescale/mpc5121ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc5121ads.o
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
deleted file mode 100644
index 741bc40382..0000000000
--- a/board/freescale/mpc5121ads/README
+++ /dev/null
@@ -1,7 +0,0 @@
-To configure for the current (Rev 3.x) ADS5121
-	make mpc5121ads_config
-This will automatically include PCI, the Real Time CLock, add backup flash
-ability and set the correct frequency and memory configuration.
-
-To configure for the older Rev 2 ADS5121 type (this will not have PCI)
-	make mpc5121ads_rev2_config
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
deleted file mode 100644
index d729056fd0..0000000000
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <net.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
-
-/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
-extern int mpc5121_nfc_chip;
-
-/* Control chips select signal on MPC5121ADS board */
-void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-{
-	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
-	u8 v;
-
-	v = in_8(csreg);
-	v |= 0x0F;
-
-	if (chip >= 0) {
-		__mpc5121_nfc_select_chip(mtd, 0);
-		v &= ~(1 << mpc5121_nfc_chip);
-	} else {
-		__mpc5121_nfc_select_chip(mtd, -1);
-	}
-
-	out_8(csreg, v);
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
-	 *
-	 * Without this the flash identification routine fails, as it needs to issue
-	 * write commands in order to establish the device ID.
-	 */
-
-#ifdef CONFIG_MPC5121ADS_REV2
-	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-#else
-	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-	} else {
-		/* running from Backup flash */
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
-	}
-#endif
-	return 0;
-}
-
-int is_micron(void){
-
-	ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar macaddr[6];
-	u32 brddate, macchk, ismicron;
-
-	/*
-	 * MAC address has serial number with date of manufacture
-	 * Boards made before Nov-08 #1180 use Micron memory;
-	 * 001e59 is the STx vendor #
-	 * Default is Elpida since it works for both but is slightly slower
-	 */
-	ismicron = 0;
-	if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
-		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
-		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
-		debug("brddate = %d\n\t", brddate);
-
-		if (macchk == 0x001e59 && brddate <= 8111180)
-			ismicron = 1;
-	} else if (brd_rev < 0x400) {
-		ismicron = 1;
-	}
-	debug("Using %s Memory settings\n\t",
-		ismicron ? "Micron" : "Elpida");
-	return(ismicron);
-}
-
-int dram_init(void)
-{
-	u32 msize = 0;
-	/*
-	 * Elpida MDDRC and initialization settings are an alternative
-	 * to the Default Micron ones for all but the earliest Rev 4 boards
-	 */
-	ddr512x_config_t elpida_mddrc_config = {
-		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
-		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
-		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
-		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
-	};
-
-	u32 elpida_init_sequence[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_ELPIDA_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_ELPIDA_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	if (is_micron()) {
-		msize = fixed_sdram(NULL, NULL, 0);
-	} else {
-		msize = fixed_sdram(&elpida_mddrc_config,
-				elpida_init_sequence,
-				sizeof(elpida_init_sequence)/sizeof(u32));
-	}
-
-	gd->ram_size = msize;
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* Set highest Slew on 9 PATA pins */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SPDIF_TXCLK */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static  iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard (void)
-{
-	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 spridr = in_be32(&im->sysconf.spridr);
-
-	printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
-		brd_rev, cpld_rev);
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	if (SVR_MJREV (spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig
deleted file mode 100644
index 97e80d5ddd..0000000000
--- a/board/ifm/ac14xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AC14XX
-
-config SYS_BOARD
-	default "ac14xx"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "ac14xx"
-
-endif
diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS
deleted file mode 100644
index 8fd74e516e..0000000000
--- a/board/ifm/ac14xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AC14XX BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/ac14xx/
-F:	include/configs/ac14xx.h
-F:	configs/ac14xx_defconfig
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
deleted file mode 100644
index 55def60417..0000000000
--- a/board/ifm/ac14xx/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ac14xx.o
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
deleted file mode 100644
index cd79e804a0..0000000000
--- a/board/ifm/ac14xx/ac14xx.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2010 ifm ecomatic GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-static int mac_diag;
-static int gpio_diag;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void gpio_configure(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-
-	im = (immap_t *) CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
-	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
-
-	/*
-	 * out_be32(&gpioregs->gpdir, 0xC2293020);
-	 * workaround for a hardware effect: configure direction in pieces,
-	 * setting all outputs at once drops the reset line too low and
-	 * makes us lose the MII connection (breaks ethernet for us)
-	 */
-	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
-	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
-
-	/* to turn from red to yellow when U-Boot runs */
-	setbits_be32(&gpioregs->gpdat, 0x00002020);
-	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
-	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
-	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
-	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
-}
-
-/* the physical location of the pins */
-#define GPIOKEY_ROW_BITMASK	0x40000000
-#define GPIOKEY_ROW_UPPER	0
-#define GPIOKEY_ROW_LOWER	1
-
-#define GPIOKEY_COL0_BITMASK	0x20000000
-#define GPIOKEY_COL1_BITMASK	0x10000000
-#define GPIOKEY_COL2_BITMASK	0x08000000
-
-/* the logical presentation of pressed keys */
-#define GPIOKEY_BIT_FNLEFT	(1 << 5)
-#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
-#define GPIOKEY_BIT_DIRUP	(1 << 3)
-#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
-#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
-#define GPIOKEY_BIT_DIRDOWN	(1 << 0)
-
-/* the hotkey combination which starts recovery */
-#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
-				 GPIOKEY_BIT_DIRDOWN)
-
-static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
-{
-
-	if (row)
-		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	else
-		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	udelay(10);
-}
-
-static u32 gpio_querykbd(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-	u32 keybits;
-	u32 input;
-
-	im = (immap_t *)CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	keybits = 0;
-
-	/* query upper row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRUP;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNRIGHT;
-
-	/* query lower row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRRIGHT;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRDOWN;
-
-	/* return bit pattern for keys */
-	return keybits;
-}
-
-/* excerpt from the recovery's hw_info.h */
-
-struct __attribute__ ((__packed__)) eeprom_layout {
-	char	magic[3];	/** 'ifm' */
-	u8	len[2];		/** content length without magic/len fields */
-	u8	version[3];	/** structure version */
-	u8	type;		/** type of PCB */
-	u8	reserved[0x37];	/** padding up to offset 0x40 */
-	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
-};
-
-#define HW_COMP_MAINCPU 2
-
-static struct eeprom_layout eeprom_content;
-static int eeprom_is_valid;
-static int eeprom_version;
-
-#define get_eeprom_field_int(name) ({ \
-	int value; \
-	int idx; \
-	value = 0; \
-	for (idx = 0; idx < sizeof(name); idx++) { \
-		value <<= 8; \
-		value |= name[idx]; \
-	} \
-	value; \
-})
-
-static int read_eeprom(void)
-{
-	return -ENOSYS;
-}
-
-int mac_read_from_eeprom(void)
-{
-	const u8 *mac;
-	const char *mac_txt;
-
-	if (read_eeprom()) {
-		printf("I2C EEPROM read failed.\n");
-		return -1;
-	}
-
-	if (!eeprom_is_valid) {
-		printf("I2C EEPROM content not valid\n");
-		return -1;
-	}
-
-	mac = NULL;
-	switch (eeprom_version) {
-	case 1:
-	case 2:
-		mac = (const u8 *)&eeprom_content.macaddress;
-		break;
-	}
-
-	if (mac && is_valid_ethaddr(mac)) {
-		eth_setenv_enetaddr("ethaddr", mac);
-		if (mac_diag) {
-			mac_txt = getenv("ethaddr");
-			if (mac_txt)
-				printf("DIAG: MAC value [%s]\n", mac_txt);
-			else
-				printf("DIAG: failed to setup MAC env\n");
-		}
-	}
-
-	return 0;
-}
-
-/*
- * BEWARE!
- * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
- * which the ADS, Aria or PDM360NG boards are using
- * (the steps outlined here refer to the Micron datasheet)
- */
-u32 sdram_init_seq[] = {
-	/* item 6, at least one NOP after CKE went high */
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 7, precharge all; item 8, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 9, extended mode register; item 10, tMRD 10ns) */
-	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 11, (base) mode register _with_ reset DLL;
-	 * item 12, tMRD (10ns)
-	 */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
-	CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 13, precharge all; item 14, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 15, auto refresh (i.e. refresh with CKE held high);
-	 * item 16, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 17, auto refresh (i.e. refresh with CKE held high);
-	 * item 18, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 21, "actually done", but make sure 200 DRAM clock cycles
-	 * have passed after DLL reset before READ requests are issued
-	 * (200 cycles at 160MHz -> 1.25 usec)
-	 */
-	/* EMPTY, optional, we don't do it */
-};
-
-int dram_init(void)
-{
-	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
-				   ARRAY_SIZE(sdram_init_seq));
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 keys;
-	char *s;
-	int want_recovery;
-
-	/* setup GPIO directions and initial values */
-	gpio_configure();
-
-	/*
-	 * enforce the start of the recovery system when
-	 * - the appropriate keys were pressed
-	 * - "some" external software told us to
-	 * - a previous installation was aborted or has failed
-	 */
-	want_recovery = 0;
-	keys = gpio_querykbd();
-	if (gpio_diag)
-		printf("GPIO keyboard status [0x%02X]\n", keys);
-	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
-		printf("detected recovery request (keyboard)\n");
-		want_recovery = 1;
-	}
-	s = getenv("want_recovery");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("detected recovery request (environment)\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_in_progress");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has not completed\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_failed");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has failed\n");
-		want_recovery = 1;
-	}
-	if (want_recovery) {
-		printf("enforced start of the recovery system\n");
-		setenv("bootcmd", "run recovery");
-	}
-
-	/*
-	 * boot the recovery system without waiting; boot the
-	 * production system without waiting by default, only
-	 * insert a pause (to provide a chance to get a prompt)
-	 * when GPIO keys were pressed during power on
-	 */
-	if (want_recovery)
-		setenv("bootdelay", "0");
-	else if (!keys)
-		setenv("bootdelay", "0");
-	else
-		setenv("bootdelay", "2");
-
-	/* get the ethernet MAC from I2C EEPROM */
-	mac_read_from_eeprom();
-
-	return 0;
-}
-
-/* setup specific IO pad configuration */
-static  iopin_t ioregs_init[] = {
-	{	/* LPC CS3 */
-		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* LPC CS1 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS2 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS4, CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
-		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO keyboard */
-		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO DN1 PF, LCD power, DN2 PF */
-		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset AS-i */
-		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset safety */
-		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset netX */
-		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO ma2 en */
-		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO SD CD, SD WP */
-		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* FEC RX DV */
-		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
-		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO safety wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO netX wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ powerfail */
-		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i PWRD */
-		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO LED0, LED1 */
-		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
-		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* DIU clk */
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* FEC TX ER, CRS */
-		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
-		offsetof(struct ioctrl512x, io_control_irq0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/*
-		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
-		 * rdx 3-0, mdio, rx clk
-		 */
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* optional: make sure PSC3 remains the serial console */
-	{	/* LPC CS6 */
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* make sure PSC4 remains available for SPI,
-	    *BUT* PSC4_1 is a GPIO kind of SS! */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	/* optional: make sure PSC5 remains available for SPI */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(1),
-	},
-	{	/* LPC TSIZ1 */
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* DIU hsync */
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU vsync */
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, part of DIU RGB */
-		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, safety UART */
-		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(0) | IO_PIN_DS(1),
-	},
-	{	/* DIU (part of) RGB[] */
-		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU data enable */
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	/* reduce LPB drive strength for improved EMI */
-	{	/* LPC OE, LPC RW */
-		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC AX03 through LPC AD00 */
-		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK */
-		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC DATA */
-		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-};
-
-int checkboard(void)
-{
-	puts("Board: ifm AC14xx\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig
deleted file mode 100644
index e9d32ddc54..0000000000
--- a/board/ifm/o2dnt2/Kconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-if TARGET_O2D
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d"
-
-endif
-
-if TARGET_O2D300
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d300"
-
-endif
-
-if TARGET_O2DNT2
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2dnt2"
-
-endif
-
-if TARGET_O2I
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2i"
-
-endif
-
-if TARGET_O2MNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2mnt"
-
-endif
-
-if TARGET_O3DNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o3dnt"
-
-endif
diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS
deleted file mode 100644
index 002f89e729..0000000000
--- a/board/ifm/o2dnt2/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-O2DNT2 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/o2dnt2/
-F:	include/configs/o2d.h
-F:	configs/O2D_defconfig
-F:	include/configs/o2d300.h
-F:	configs/O2D300_defconfig
-F:	include/configs/o2dnt2.h
-F:	configs/O2DNT2_defconfig
-F:	configs/O2DNT2_RAMBOOT_defconfig
-F:	include/configs/o2i.h
-F:	configs/O2I_defconfig
-F:	include/configs/o2mnt.h
-F:	configs/O2MNT_defconfig
-F:	configs/O2MNT_O2M110_defconfig
-F:	configs/O2MNT_O2M112_defconfig
-F:	configs/O2MNT_O2M113_defconfig
-F:	include/configs/o3dnt.h
-F:	configs/O3DNT_defconfig
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
deleted file mode 100644
index 64d6ba8c55..0000000000
--- a/board/ifm/o2dnt2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= o2dnt2.o
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
deleted file mode 100644
index 7770806bd2..0000000000
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * Partially derived from board code for digsyMTC,
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <net.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-
-enum ifm_sensor_type {
-	O2DNT		= 0x00,	/* !< O2DNT 32MB */
-	O2DNT2		= 0x01,	/* !< O2DNT2 64MB */
-	O3DNT		= 0x02,	/* !< O3DNT 32MB */
-	O3DNT_MIN	= 0x40,	/* !< O3DNT Minerva 32MB */
-	UNKNOWN		= 0xff,	/* !< Unknow sensor */
-};
-
-static enum ifm_sensor_type gt_ifm_sensor_type;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, control | 0x80000004);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-int dram_init(void)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-	if (gt_ifm_sensor_type == O2DNT2) {
-		/* activate SDRAM CS1 */
-		setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
-	}
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
-	out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mmap_ctl->sdram0,
-			 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32(&mmap_ctl->sdram0, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	}
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32(&mmap_ctl->sdram1, (dramsize |
-			 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32(&sdram->sdelay, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-
-#define GPT_GPIO_IN	0x4
-
-int checkboard(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	unsigned char board_config = 0;
-	int i;
-
-	/* switch gpt0 - gpt7 to input */
-	for (i = 0; i < 7; i++)
-		out_be32(&gpt[i].emsr, GPT_GPIO_IN);
-
-	/* get configuration byte on timer-port */
-	for (i = 0; i < 7; i++)
-		board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
-
-	puts("Board: ");
-
-	switch (board_config) {
-	case 0:
-		puts("O2DNT\n");
-		gt_ifm_sensor_type = O2DNT;
-		break;
-	case 1:
-		puts("O3DNT\n");
-		gt_ifm_sensor_type = O3DNT;
-		break;
-	case 2:
-		puts("O2DNT2\n");
-		gt_ifm_sensor_type = O2DNT2;
-		break;
-	case 64:
-		puts("O3DNT Minerva\n");
-		gt_ifm_sensor_type = O3DNT_MIN;
-		break;
-	default:
-		puts("Unknown\n");
-		gt_ifm_sensor_type = UNKNOWN;
-		break;
-	}
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in flash.
-	 */
-	clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-	return 0;
-}
-
-#define MIIM_LXT971_LED_CFG_REG		0x14
-#define LXT971_LED_CFG_LINK_STATUS	0x4000
-#define LXT971_LED_CFG_RX_TX_ACTIVITY	0x0700
-#define LXT971_LED_CFG_LINK_ACTIVITY	0x00D0
-#define LXT971_LED_CFG_PULSE_STRETCH	0x0002
-/*
- * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
- */
-void reset_phy(void)
-{
-	/*
-	 * Set LED configuration bits.
-	 * It can't be done in misc_init_r() since FEC is not
-	 * initialized at this time. Therefore we do it here.
-	 */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
-			LXT971_LED_CFG_LINK_STATUS |
-			LXT971_LED_CFG_RX_TX_ACTIVITY |
-			LXT971_LED_CFG_LINK_ACTIVITY |
-			LXT971_LED_CFG_PULSE_STRETCH);
-}
-
-#if defined(CONFIG_POST)
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
-	 * CODEC or UART mode. Consumer IrDA should still be possible.
-	 */
-	clrbits_be32(&gpio->port_config, 0x07000000);
-	setbits_be32(&gpio->port_config, 0x03000000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	setbits_be32(&gpio->simple_gpioe, 0x20000000);
-
-	/* Configure GPIO_IRDA_1 as input */
-	clrbits_be32(&gpio->simple_ddr, 0x20000000);
-
-	return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
-}
-#endif
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size(phys_addr_t base, int banknum);
-
-/* Update the flash baseaddr settings */
-int update_flash_size(int flash_size)
-{
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t *dev;
-	int i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig
deleted file mode 100644
index 94a41f01a5..0000000000
--- a/board/inka4x0/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_INKA4X0
-
-config SYS_BOARD
-	default "inka4x0"
-
-config SYS_CONFIG_NAME
-	default "inka4x0"
-
-endif
diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS
deleted file mode 100644
index e8cec73a1a..0000000000
--- a/board/inka4x0/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-INKA4X0 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/inka4x0/
-F:	include/configs/inka4x0.h
-F:	configs/inka4x0_defconfig
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
deleted file mode 100644
index c9a3540799..0000000000
--- a/board/inka4x0/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2009
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= inka4x0.o inkadiag.o
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
deleted file mode 100644
index 88cae59e8f..0000000000
--- a/board/inka4x0/inka4x0.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
- *
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_DDR_MT46V16M16)
-#include "mt46v16m16-75.h"
-#elif defined(CONFIG_SDR_MT48LC16M16A2)
-#include "mt48lc16m16a2-75.h"
-#elif defined(CONFIG_DDR_MT46V32M16)
-#include "mt46v32m16.h"
-#elif defined(CONFIG_DDR_HYB25D512160BF)
-#include "hyb25d512160bf.h"
-#elif defined(CONFIG_DDR_K4H511638C)
-#include "k4h511638c.h"
-#else
-#error "INKA4x0 SDRAM: invalid chip type specified!"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32(&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm     *cdm =
-		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	long test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
-	out_be32(&mm->sdram1, 0x40000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mm->sdram0, 0x13 +
-			 __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32(&mm->sdram0, 0); /* disabled */
-	}
-
-	out_be32(&mm->sdram1, dramsize); /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: INKA 4X0\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT (CS0) cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
-}
-
-int misc_init_f (void)
-{
-	volatile struct mpc5xxx_gpio	*gpio    =
-		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
-	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	volatile struct mpc5xxx_gpt	*gpt;
-	char tmp[10];
-	int i, br;
-
-	i = getenv_f("brightness", tmp, sizeof(tmp));
-	br = (i > 0)
-		? (int) simple_strtoul (tmp, NULL, 10)
-		: CONFIG_SYS_BRIGHTNESS;
-	if (br > 255)
-		br = 255;
-
-	/* Initialize GPIO output pins.
-	 */
-	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
-	for (i = 0; i <= 5; i++) {
-		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
-		out_be32(&gpt->emsr, 0x34);
-	}
-
-	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
-	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
-	out_be32(&gpt->emsr,  0);		/* Disable */
-	out_be32(&gpt->cir,   0x020000fe);
-	out_be32(&gpt->pwmcr, (br << 16));
-	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */
-
-	/* Configure PSC3_6,7 as GPIO output */
-	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-
-	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Set LR mirror bit because it is low-active */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
-
-	/* Reset Coral-P graphics controller */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Enable display backlight */
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
-
-	/*
-	 * Configure three wire serial interface to RTC (PSC1_4,
-	 * PSC2_4, PSC3_4, PSC3_5)
-	 */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
-	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
-
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
deleted file mode 100644
index 4c43205129..0000000000
--- a/board/inka4x0/inkadiag.c
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * (C) Copyright 2008, 2009 Andreas Pfefferle,
- *     DENX Software Engineering, ap@denx.de.
- * (C) Copyright 2009 Detlev Zundel,
- *     DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <config.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include <command.h>
-
-/* This is needed for the includes in ns16550.h */
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#include <ns16550.h>
-
-#define GPIO_BASE		((u_char *)CONFIG_SYS_CS3_START)
-
-#define DIGIN_TOUCHSCR_MASK	0x00003000	/* Inputs 12-13 */
-#define DIGIN_KEYB_MASK		0x00010000	/* Input 16 */
-
-#define DIGIN_DRAWER_SW1	0x00400000	/* Input 22 */
-#define DIGIN_DRAWER_SW2	0x00800000	/* Input 23 */
-
-#define DIGIO_LED0		0x00000001	/* Output 0 */
-#define DIGIO_LED1		0x00000002	/* Output 1 */
-#define DIGIO_LED2		0x00000004	/* Output 2 */
-#define DIGIO_LED3		0x00000008	/* Output 3 */
-#define DIGIO_LED4		0x00000010	/* Output 4 */
-#define DIGIO_LED5		0x00000020	/* Output 5 */
-
-#define DIGIO_DRAWER1		0x00000100	/* Output 8 */
-#define DIGIO_DRAWER2		0x00000200	/* Output 9 */
-
-#define SERIAL_PORT_BASE	((u_char *)CONFIG_SYS_CS2_START)
-
-#define PSC_OP1_RTS	0x01
-#define PSC_OP0_RTS	0x01
-
-/*
- * Table with supported baudrates (defined in inka4x0.h)
- */
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
-
-static unsigned int inka_digin_get_input(void)
-{
-	return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
-		in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
-}
-
-#define LED_HIGH(NUM)							\
-	do {								\
-		setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define LED_LOW(NUM)							\
-	do {								\
-		clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define CHECK_LED(NUM) \
-    do { \
-	    if (state & (1 << NUM)) {		\
-		    LED_HIGH(NUM);		\
-	    } else {				\
-		    LED_LOW(NUM);		\
-	    }					\
-    } while (0)
-
-static void inka_digio_set_output(unsigned int state, int which)
-{
-	volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (which == 0) {
-		/* other */
-		CHECK_LED(0);
-		CHECK_LED(1);
-		CHECK_LED(2);
-		CHECK_LED(3);
-		CHECK_LED(4);
-		CHECK_LED(5);
-	} else {
-		if (which == 1) {
-			/* drawer1 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-			}
-		}
-		if (which == 2) {
-			/* drawer 2 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-			}
-		}
-	}
-	udelay(1);
-}
-
-static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
-			  char * const argv[]) {
-	unsigned int state, val;
-
-	switch (argc) {
-	case 3:
-		/* Write a value */
-		val = simple_strtol(argv[2], NULL, 16);
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			inka_digio_set_output(val, 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			inka_digio_set_output(val, 2);
-		} else if (strcmp(argv[1], "other") == 0)
-			inka_digio_set_output(val, 0);
-		else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		/* fall through */
-	case 2:
-		/* Read a value */
-		state = inka_digin_get_input();
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
-		} else if (strcmp(argv[1], "other") == 0) {
-			val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
-				| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
-		} else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		printf("exit code: 0x%X\n", val);
-		return 0;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return -1;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
-{
-	unsigned long baseclk;
-	int div;
-
-	/* reset PSC */
-	out_8(&psc->command, PSC_SEL_MODE_REG_1);
-
-	/* select clock sources */
-
-	out_be16(&psc->psc_clock_select, 0);
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* switch to UART mode */
-	out_be32(&psc->sicr, 0);
-
-	/* configure parity, bit length and so on */
-
-	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
-	out_8(&psc->mode, PSC_MODE_ONE_STOP);
-
-	/* set up UART divisor */
-	div = (baseclk + (baudrate / 2)) / baudrate;
-	out_8(&psc->ctur, (div >> 8) & 0xff);
-	out_8(&psc->ctlr, div & 0xff);
-
-	/* disable all interrupts */
-	out_be16(&psc->psc_imr, 0);
-
-	/* reset and enable Rx/Tx */
-	out_8(&psc->command, PSC_RST_RX);
-	out_8(&psc->command, PSC_RST_TX);
-	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	return 0;
-}
-
-static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
-{
-	/* Wait 1 second for last character to go. */
-	int i = 0;
-
-	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
-		udelay(10);
-	psc->psc_buffer_8 = c;
-
-}
-
-static int ser_getc(volatile struct mpc5xxx_psc *psc)
-{
-	/* Wait for a character to arrive. */
-	int i = 0;
-
-	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
-		udelay(10);
-
-	return in_8(&psc->psc_buffer_8);
-}
-
-static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-	volatile struct NS16550 *uart;
-	volatile struct mpc5xxx_psc *psc;
-	unsigned int num, mode;
-	int combrd, baudrate, i, j, len;
-	int address;
-
-	if (argc < 5)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	num = simple_strtol(argv[0], NULL, 0);
-	if (num < 0 || num > 11) {
-		printf("invalid argument for num: %d\n", num);
-		return -1;
-	}
-
-	mode = simple_strtol(argv[1], NULL, 0);
-
-	combrd = 0;
-	baudrate = simple_strtoul(argv[2], NULL, 10);
-	for (i=0; i<N_BAUDRATES; ++i) {
-		if (baudrate == baudrate_table[i])
-			break;
-	}
-	if (i == N_BAUDRATES) {
-		printf("## Baudrate %d bps not supported\n",
-		       baudrate);
-		return 1;
-	}
-	combrd = 115200 / baudrate;
-
-	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
-
-	printf("Testing uart %d.\n\n", num);
-
-	if ((num >= 0) && (num <= 7)) {
-		if (mode & 1) {
-			/* turn on 'loopback' mode */
-			out_8(&uart->mcr, UART_MCR_LOOP);
-		} else {
-			/*
-			 * establish the UART's operational parameters
-			 * set DLAB=1, so rbr accesses DLL
-			 */
-			out_8(&uart->lcr, UART_LCR_DLAB);
-			/* set baudrate */
-			out_8(&uart->rbr, combrd);
-			/* set data-format: 8-N-1 */
-			out_8(&uart->lcr, UART_LCR_WLS_8);
-		}
-
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&uart->mcr, UART_MCR_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
-				return -1;
-		}
-		if (mode & 4) {
-			/* set data terminal ready */
-			out_8(&uart->mcr, UART_MCR_DTR);
-			udelay(10);
-			/* check data set ready and carrier detect */
-			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
-			    != (UART_MSR_DSR | UART_MSR_DCD))
-				return -1;
-		}
-
-		/* write each message-character, read it back, and display it */
-		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			out_8(&uart->rbr, argv[3][i]);
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			printf("%c", in_8(&uart->rbr));
-		}
-		printf("\n\n");
-		out_8(&uart->mcr, 0x00);
-	} else {
-		address = 0;
-
-		switch (num) {
-		case 8:
-			address = MPC5XXX_PSC6;
-			break;
-		case 9:
-			address = MPC5XXX_PSC3;
-			break;
-		case 10:
-			address = MPC5XXX_PSC2;
-			break;
-		case 11:
-			address = MPC5XXX_PSC1;
-			break;
-		}
-		psc = (struct mpc5xxx_psc *)address;
-		ser_init(psc, simple_strtol(argv[2], NULL, 0));
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&psc->op0, PSC_OP0_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
-				return -1;
-		}
-		len = strlen(argv[3]);
-		for (i = 0; i < len; ++i) {
-			ser_putc(psc, argv[3][i]);
-			printf("%c", ser_getc(psc));
-		}
-		printf("\n\n");
-	}
-	return 0;
-}
-
-#define BUZZER_GPT	(MPC5XXX_GPT + 0x60)	/* GPT6 */
-static void buzzer_turn_on(unsigned int freq)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	const u32 prescale = gd->arch.ipb_clk / freq / 128;
-	const u32 count = 128;
-	const u32 width = 64;
-
-	gpt->cir = (prescale << 16) | count;
-	gpt->pwmcr = width << 16;
-	gpt->emsr = 3;		/* Timer enabled for PWM */
-}
-
-static void buzzer_turn_off(void)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	gpt->emsr = 0;
-}
-
-static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-
-	unsigned int period, freq;
-	int prev, i;
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	period = simple_strtol(argv[0], NULL, 0);
-	if (!period)
-		printf("Zero period is senseless\n");
-	argc--;
-	argv++;
-
-	freq = simple_strtol(argv[0], NULL, 0);
-	/* avoid zero prescale in buzzer_turn_on() */
-	if (freq > gd->arch.ipb_clk / 128) {
-		printf("%dHz exceeds maximum (%ldHz)\n", freq,
-		       gd->arch.ipb_clk / 128);
-	} else if (!freq)
-		printf("Zero frequency is senseless\n");
-	else
-		buzzer_turn_on(freq);
-
-	clear_ctrlc();
-	prev = disable_ctrlc(0);
-
-	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
-
-	i = 0;
-	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
-		udelay(period);
-
-	clear_ctrlc();
-	disable_ctrlc(prev);
-
-	buzzer_turn_off();
-
-	return 0;
-}
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-cmd_tbl_t cmd_inkadiag_sub[] = {
-	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
-	 "<drawer1|drawer2|other> [value] - get or set specified signal"),
-	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
-	 "<num> <mode> <baudrate> <msg>  - test uart num [0..11] in mode\n"
-	 "and baudrate with msg"),
-	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
-	 "<period> <freq> - turn buzzer on for period ms with freq hz"),
-	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
-	 "[command] - get help for command"),
-};
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
-			    int argc, char * const argv[]) {
-	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
-			     cmd_tbl_t *cmdtp, int flag,
-			     int argc, char * const argv[]);
-	/* do_help prints command name - we prepend inkadiag to our subcommands! */
-#ifdef CONFIG_SYS_LONGHELP
-	puts ("inkadiag ");
-#endif
-	return _do_help(&cmd_inkadiag_sub[0],
-		ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
-}
-
-static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[]) {
-	cmd_tbl_t *c;
-
-	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
-
-	if (c) {
-		argc--;
-		argv++;
-		return c->cmd(c, flag, argc, argv);
-	} else {
-		/* Unrecognized command */
-		return cmd_usage(cmdtp);
-	}
-}
-
-U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
-	   "inkadiag - inka diagnosis\n",
-	   "[inkadiag what ...]\n"
-	   "    - perform a diagnosis on inka hardware\n"
-	   "'inkadiag' performs hardware tests.");
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
deleted file mode 100644
index 054ddafd59..0000000000
--- a/board/inka4x0/k4h511638c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
deleted file mode 100644
index 23fc6f06be..0000000000
--- a/board/inka4x0/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
deleted file mode 100644
index f16f450d01..0000000000
--- a/board/inka4x0/mt46v32m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig
deleted file mode 100644
index 1cf2275d81..0000000000
--- a/board/intercontrol/digsy_mtc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DIGSY_MTC
-
-config SYS_BOARD
-	default "digsy_mtc"
-
-config SYS_VENDOR
-	default "intercontrol"
-
-config SYS_CONFIG_NAME
-	default "digsy_mtc"
-
-endif
diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS
deleted file mode 100644
index c83ebcdab9..0000000000
--- a/board/intercontrol/digsy_mtc/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-DIGSY_MTC BOARD
-M:	Werner Pfister <Pfister_Werner@intercontrol.de>
-S:	Maintained
-F:	board/intercontrol/digsy_mtc/
-F:	include/configs/digsy_mtc.h
-F:	configs/digsy_mtc_defconfig
-F:	configs/digsy_mtc_RAMBOOT_defconfig
-F:	configs/digsy_mtc_rev5_defconfig
-F:	configs/digsy_mtc_rev5_RAMBOOT_defconfig
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
deleted file mode 100644
index 4d13eadf5b..0000000000
--- a/board/intercontrol/digsy_mtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= digsy_mtc.o
-obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c
deleted file mode 100644
index 2ffa8bfe40..0000000000
--- a/board/intercontrol/digsy_mtc/cmd_disp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2011 DENX Software Engineering,
- * Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <asm/io.h>
-
-#define GPIO_USB1_0	0x00010000
-
-static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (argc < 2) {
-		printf("%s\n",
-		       in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
-		return 0;
-	}
-
-	if (!strncmp(argv[1], "on", 2)) {
-		setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else if (!strncmp(argv[1], "off", 3)) {
-		clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else {
-		cmd_usage(cmdtp);
-		return 1;
-	}
-	return 0;
-}
-
-U_BOOT_CMD(disp, 2, 1, cmd_disp,
-		"disp [on/off] - switch display on/off",
-		"\n    - print display on/off status\n"
-		"on\n    - turn on\n"
-		"off\n    - turn off\n"
-);
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
deleted file mode 100644
index 6c33eeb022..0000000000
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2009
- * Modified for InterControl digsyMTC MPC5200 board by
- * Frank Bodammer, GCD Hard- & Software GmbH,
- *                 frank.bodammer@gcd-solutions.de
- *
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "eeprom.h"
-#if defined(CONFIG_DIGSY_REV5)
-#include "is45s16800a2.h"
-#include <mtd/cfi_flash.h>
-#include <flash.h>
-#else
-#include "is42s16800a-7t.h"
-#endif
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mb862xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int usb_cpu_init(void);
-
-#if defined(CONFIG_DIGSY_REV5)
-/*
- * The M29W128GH needs a special reset command function,
- * details see the doc/README.cfi file
- */
-void flash_cmd_reset(flash_info_t *info)
-{
-	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
-}
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
-
-	/* find RAM size using SDRAM CS1 only */
-	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-			0x08000000);
-		dramsize2 = test1;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
-			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: InterControl digsyMTC");
-#if defined(CONFIG_DIGSY_REV5)
-	puts (" rev5");
-#endif
-	if (i > 0) {
-		puts(", ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-#if defined(CONFIG_VIDEO)
-
-#define GPIO_USB1_0		0x00010000	/* Power-On pin */
-#define GPIO_USB1_9		0x08		/* PX_~EN pin */
-
-#define GPIO_EE_DO		0x10		/* PSC6_0 (DO) pin */
-#define GPIO_EE_CTS		0x20		/* PSC6_1 (CTS) pin */
-#define GPIO_EE_DI		0x10000000	/* PSC6_2 (DI) pin */
-#define GPIO_EE_CLK		0x20000000	/* PSC6_3 (CLK) pin */
-
-#define GPT_GPIO_ON		0x00000034	/* GPT as simple GPIO, high */
-
-static void exbo_hw_init(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_wu_gpio *wu_gpio =
-				(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	/* configure IrDA pins (PSC6 port) as gpios */
-	gpio->port_config &= 0xFF8FFFFF;
-
-	/* Init for USB1_0, EE_CLK and EE_DI - Low */
-	setbits_be32(&gpio->simple_ddr,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_ode,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_dvo,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	setbits_be32(&gpio->simple_gpioe,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-
-	/* Init for EE_DO, EE_CTS - Input */
-	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
-	setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
-
-	/* Init for PX_~EN (USB1_9) - High */
-	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
-	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
-	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
-	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
-	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
-
-	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
-	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
-	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
-	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
-
-	/* Power-On camera supply */
-	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-}
-#else
-static inline void exbo_hw_init(void) {}
-#endif /* CONFIG_VIDEO */
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process.  Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS1 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-
-	return (0);
-}
-
-void board_get_enetaddr (uchar * enet)
-{
-	ushort read = 0;
-	ushort addr_of_eth_addr = 0;
-	ushort len_sys = 0;
-	ushort len_sys_cfg = 0;
-
-	/* check identification word */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
-	if (read != EEPROM_IDENT)
-		return;
-
-	/* calculate offset of config area */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
-		(uchar *)&len_sys_cfg, 2);
-	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
-	if (addr_of_eth_addr >= EEPROM_LEN)
-		return;
-
-	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
-}
-
-int misc_init_r(void)
-{
-	pci_dev_t devbusfn;
-	uchar enetaddr[6];
-
-	/* check if graphic extension board is present */
-	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
-				   PCI_DEVICE_ID_CORAL_PA, 0);
-	if (devbusfn != -1)
-		exbo_hw_init();
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_IDE
-
-#ifdef CONFIG_IDE_RESET
-
-void init_ide_reset(void)
-{
-	debug ("init_ide_reset\n");
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-}
-
-void ide_set_reset(int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	/* set gpio output value to 0 */
-	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-	udelay(10000);
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-}
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_IDE */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static void ft_delete_node(void *fdt, const char *compat)
-{
-	int off = -1;
-	int ret;
-
-	off = fdt_node_offset_by_compatible(fdt, -1, compat);
-	if (off < 0) {
-		printf("Could not find %s node.\n", compat);
-		return;
-	}
-
-	ret = fdt_del_node(fdt, off);
-	if (ret < 0)
-		printf("Could not delete %s node.\n", compat);
-}
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size (phys_addr_t base, int banknum);
-
-/* Update the Flash Baseaddr settings */
-int update_flash_size (int flash_size)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t	*dev;
-	int	i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-	/*
-	 * There are 2 RTC nodes in the DTS, so remove
-	 * the unneeded node here.
-	 */
-#if defined(CONFIG_DIGSY_REV5)
-	ft_delete_node(blob, "dallas,ds1339");
-#else
-	ft_delete_node(blob, "mc,rv3029c2");
-#endif
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
deleted file mode 100644
index 17bd034072..0000000000
--- a/board/intercontrol/digsy_mtc/eeprom.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2009 Semihalf.
- * Written by: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef CMD_EEPROM_H
-#define CMD_EEPROM_H
-
-#define EEPROM_ADDR		CONFIG_SYS_I2C_EEPROM_ADDR
-#define EEPROM_LEN		1024	/* eeprom length */
-#define EEPROM_IDENT		2408	/* identification word */
-#define EEPROM_ADDR_IDENT	0	/* identification word offset */
-#define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
-#define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
-#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
-
-#endif
diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
deleted file mode 100644
index c555d2d623..0000000000
--- a/board/intercontrol/digsy_mtc/is42s16800a-7t.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x505F0000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h
deleted file mode 100644
index c42ba38e34..0000000000
--- a/board/intercontrol/digsy_mtc/is45s16800a2.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * based on:
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x50470000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig
deleted file mode 100644
index 34e094d79d..0000000000
--- a/board/ipek01/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IPEK01
-
-config SYS_BOARD
-	default "ipek01"
-
-config SYS_CONFIG_NAME
-	default "ipek01"
-
-endif
diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS
deleted file mode 100644
index 906d39ef80..0000000000
--- a/board/ipek01/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IPEK01 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ipek01/
-F:	include/configs/ipek01.h
-F:	configs/ipek01_defconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
deleted file mode 100644
index a786ab2118..0000000000
--- a/board/ipek01/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ipek01.o
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
deleted file mode 100644
index 133db8c6bd..0000000000
--- a/board/ipek01/ipek01.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * (C) Copyright 2009
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <mb862xx.h>
-#include <video_fb.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-/* mt46v16m16-75 */
-#ifdef CONFIG_MPC5200_DDR
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-#else
-#error SDRAM is not supported on this board
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32 (&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
-	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start (0);
-	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start (1);
-	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start (0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		out_be32 (&mmap_ctl->sdram0,
-			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
-	else
-		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	out_be32 (&sdram->sdelay, 0x04);
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: IPEK01 \n");
-	return 0;
-}
-
-void flash_preinit (void)
-{
-	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
-}
-
-void flash_afterinit (ulong start, ulong size)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_BOOT_ROM)
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
-#else
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->boot_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
-	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
-	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
-#endif
-}
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-int misc_init_r (void)
-{
-	/* adjust flash start */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	return (0);
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init (struct pci_controller *);
-
-void pci_init_board (void)
-{
-	pci_mpc5xxx_init (&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup (blob, bd);
-	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_VIDEO
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs[] = {
-	{0x0100, 0x00000900},
-	{0x0020, 0x80190257},
-	{0x0024, 0x00000000},
-	{0x0028, 0x00000000},
-	{0x002c, 0x00000000},
-	{0x0110, 0x00000000},
-	{0x0114, 0x00000000},
-	{0x0118, 0x02570320},
-	{0x0004, 0x041f0000},
-	{0x0008, 0x031f031f},
-	{0x000c, 0x067f0347},
-	{0x0010, 0x02780000},
-	{0x0014, 0x0257025c},
-	{0x0018, 0x00000000},
-	{0x001c, 0x02570320},
-	{0x0100, 0x80010900},
-	{0x0, 0x0}
-};
-
-const gdc_regs *board_get_regs (void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init (void)
-{
-	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
-		return 0;
-
-	mb862xx.winSizeX = 800;
-	mb862xx.winSizeY = 600;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-	mb862xx.gdfBytesPP = 2;
-
-	return CONFIG_SYS_LIME_BASE;
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy (info, " Board: IPEK01");
-	else
-		info[0] = '\0';
-}
-#endif
-#endif /* CONFIG_VIDEO */
diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig
deleted file mode 100644
index d71acbbc4d..0000000000
--- a/board/jupiter/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_JUPITER
-
-config SYS_BOARD
-	default "jupiter"
-
-config SYS_CONFIG_NAME
-	default "jupiter"
-
-endif
diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS
deleted file mode 100644
index 5a79a616cc..0000000000
--- a/board/jupiter/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JUPITER BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/jupiter/
-F:	include/configs/jupiter.h
-F:	configs/jupiter_defconfig
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
deleted file mode 100644
index 4d3ef9ed7a..0000000000
--- a/board/jupiter/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= jupiter.o
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
deleted file mode 100644
index 52d2766e9a..0000000000
--- a/board/jupiter/jupiter.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-
-#define SDRAM_DDR	0
-#if 1
-/* Settings Icecube */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-#else
-/*Settings Jupiter UB 1.0.0 */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0xD04F0000
-#define SDRAM_CONFIG1	0xf7277f00
-#define SDRAM_CONFIG2	0x88b70004
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Sauter (Jupiter)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-int board_early_init_r (void)
-{
-	flash_preinit ();
-	return 0;
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x1000000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-}
-
-int update_flash_size (int flash_size)
-{
-	flash_afterinit (flash_size);
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig
deleted file mode 100644
index f624f6c95f..0000000000
--- a/board/motionpro/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MOTIONPRO
-
-config SYS_BOARD
-	default "motionpro"
-
-config SYS_CONFIG_NAME
-	default "motionpro"
-
-endif
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
deleted file mode 100644
index 2f8b5cb580..0000000000
--- a/board/motionpro/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MOTIONPRO BOARD
-#M:	-
-S:	Maintained
-F:	board/motionpro/
-F:	include/configs/motionpro.h
-F:	configs/motionpro_defconfig
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
deleted file mode 100644
index 898a384c39..0000000000
--- a/board/motionpro/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= motionpro.o
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
deleted file mode 100644
index 7883a179e8..0000000000
--- a/board/motionpro/motionpro.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
- * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
- * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
- * Also changed the refresh for 100MHz operation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <miiphy.h>
-#include <libfdt.h>
-
-#if defined(CONFIG_LED_STATUS)
-#include <status_led.h>
-#endif /* CONFIG_LED_STATUS */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Kollmorgen DPR initialization data */
-struct init_elem {
-	unsigned long addr;
-	unsigned len;
-	char *data;
-	} init_seq[] = {
-		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
-		{0x500003F0, 2, "\x00\x00"},
-		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
-	};
-
-/*
- * Initialize Kollmorgen DPR
- */
-static void kollmorgen_init(void)
-{
-	unsigned i, j;
-	vu_char *p;
-
-	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
-		p = (vu_char *)init_seq[i].addr;
-		for (j = 0; j < init_seq[i].len; ++j)
-			*(p + j) = *(init_seq[i].data + j);
-	}
-
-	printf("DPR:   Kollmorgen DPR initialized\n");
-}
-
-
-/*
- * Early board initalization.
- */
-int board_early_init_r(void)
-{
-	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
-
-	/* Initialize Kollmorgen DPR */
-	kollmorgen_init();
-
-	return 0;
-}
-
-
-/*
- * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
- * PHY goes into FX mode.  To take it out of the FX mode and switch into
- * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
- * Register.
- */
-void reset_phy(void)
-{
-	unsigned short mode_control;
-
-	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
-			mode_control & 0xfffe);
-	return;
-}
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-int dram_init(void)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* According to AN3221 (MPC5200B SDRAM Initialization and
-	 * Configuration), the SDelay register must be written a value of
-	 * 0x00000004 as the first step of the SDRAM contorller configuration.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 and disable it */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
-
-#else /* !CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* return total ram size */
-	gd->ram_size = dramsize;
-
-	return 0;
-}
-
-
-int checkboard(void)
-{
-	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
-	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
-	return 0;
-}
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-#if defined(CONFIG_LED_STATUS)
-vu_long *regcode_to_regaddr(led_id_t regcode)
-{
-	/* GPT Enable and Mode Select Register address */
-	vu_long *reg_translate[] = {
-					(vu_long *)MPC5XXX_GPT6_ENABLE,
-					(vu_long *)MPC5XXX_GPT7_ENABLE,
-				   };
-
-	if (ARRAY_SIZE(reg_translate) <= regcode)
-		return NULL;
-	return reg_translate[regcode];
-}
-
-void __led_init(led_id_t regcode, int state)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	*regaddr |= ENABLE_GPIO_OUT;
-
-	if (state == CONFIG_LED_STATUS_ON)
-		*((vu_long *) regaddr) |= LED_ON;
-	else
-		*((vu_long *) regaddr) &= ~LED_ON;
-}
-
-void __led_set(led_id_t regcode, int state)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	if (state == CONFIG_LED_STATUS_ON)
-		*regaddr |= LED_ON;
-	else
-		*regaddr &= ~LED_ON;
-}
-
-void __led_toggle(led_id_t regcode)
-{
-	vu_long *regaddr = regcode_to_regaddr(regcode);
-
-	*regaddr ^= LED_ON;
-}
-#endif /* CONFIG_LED_STATUS */
diff --git a/board/munices/Kconfig b/board/munices/Kconfig
deleted file mode 100644
index 019aaae3e9..0000000000
--- a/board/munices/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MUNICES
-
-config SYS_BOARD
-	default "munices"
-
-config SYS_CONFIG_NAME
-	default "munices"
-
-endif
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
deleted file mode 100644
index 50d3e7ebda..0000000000
--- a/board/munices/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MUNICES BOARD
-#M:	-
-S:	Maintained
-F:	board/munices/
-F:	include/configs/munices.h
-F:	configs/munices_defconfig
diff --git a/board/munices/Makefile b/board/munices/Makefile
deleted file mode 100644
index d16e2a1fa2..0000000000
--- a/board/munices/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= munices.o
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa2ca..0000000000
--- a/board/munices/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/munices/munices.c b/board/munices/munices.c
deleted file mode 100644
index 468eb3723e..0000000000
--- a/board/munices/munices.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include "mt48lc16m16a2-75.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR && SDRAM_TAPDELAY
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: MUNICes\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig
deleted file mode 100644
index 33173a0a2a..0000000000
--- a/board/pdm360ng/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PDM360NG
-
-config SYS_BOARD
-	default "pdm360ng"
-
-config SYS_CONFIG_NAME
-	default "pdm360ng"
-
-endif
diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS
deleted file mode 100644
index 5c99f59e8f..0000000000
--- a/board/pdm360ng/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PDM360NG BOARD
-M:	Michael Weiss <michael.weiss@ifm.com>
-S:	Maintained
-F:	board/pdm360ng/
-F:	include/configs/pdm360ng.h
-F:	configs/pdm360ng_defconfig
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
deleted file mode 100644
index 99201a41f6..0000000000
--- a/board/pdm360ng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pdm360ng.o
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
deleted file mode 100644
index 371bcd9e6b..0000000000
--- a/board/pdm360ng/pdm360ng.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
- *
- * (C) Copyright 2009-2010
- * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#include <flash.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <serial.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[];
-ulong flash_get_size (phys_addr_t base, int banknum);
-
-sdram_conf_t mddrc_config[] = {
-	{
-		(512 << 20),	/* 512 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG,
-			CONFIG_SYS_MDDRC_TIME_CFG0,
-			CONFIG_SYS_MDDRC_TIME_CFG1,
-			CONFIG_SYS_MDDRC_TIME_CFG2
-		}
-	},
-	{
-		(128 << 20),	/* 128 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
-		}
-	},
-};
-
-int dram_init(void)
-{
-	int i;
-	u32 msize = 0;
-	u32 pdm360ng_init_seq[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_DDRCMD_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_DDRCMD_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
-		msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
-				    ARRAY_SIZE(pdm360ng_init_seq));
-		if (msize == mddrc_config[i].size)
-			break;
-	}
-
-	gd->ram_size = msize;
-
-	return 0;
-}
-
-static int set_lcd_brightness(char *);
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	/*
-	 * Re-configure flash setup using auto-detected info
-	 */
-	if (flash_info[1].size > 0) {
-		out_be32(&im->sysconf.lpcs1aw,
-			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
-			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
-				  flash_info[1].size));
-		sync_law(&im->sysconf.lpcs1aw);
-		/*
-		 * Re-check to get correct base address
-		 */
-		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
-	} else {
-		/* Disable Bank 1 */
-		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
-		sync_law(&im->sysconf.lpcs1aw);
-	}
-
-	out_be32(&im->sysconf.lpcs0aw,
-		CSAW_START(gd->bd->bi_flashstart) |
-		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
-	sync_law(&im->sysconf.lpcs0aw);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size (gd->bd->bi_flashstart, 0);
-
-	/*
-	 * Re-do flash protection upon new addresses
-	 */
-	flash_protect (FLAG_PROTECT_CLEAR,
-		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[0]);
-
-	/* Monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-		       &flash_info[0]);
-
-	/* Environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	/* Redundant environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR_REDUND,
-		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-#endif
-
-#ifdef CONFIG_FSL_DIU_FB
-	set_lcd_brightness(0);
-	/* Switch LCD-Backlight and LVDS-Interface on */
-	setbits_be32(&im->gpio.gpdir, 0x01040000);
-	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
-#endif
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=LPC_CS4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO10 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=CAN3_TX */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO14 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
-	/* DIU_LD22-DIU_LD23 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
-	/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
-	/* VIU_DATA0-VIU_DATA2 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_TXD_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
-	/* VIU_DATA3, VIU_DATA4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
-	/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
-	/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
-	/* DIU_LD00-DIU_LD21 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
-	/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=CAN3_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* Sets lowest slew on 2 CAN_TX Pins*/
-	{
-		offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
-	/* CAN4_TX, CAN4_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
-	/* GPIO8, GPIO9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
-	/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
-	/* FEC_RXD_3, FEC_RXD_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO17 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
-	/* GPIO2, GPIO20, GPIO21 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_PIX_CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
-	/* GPIO24, GPIO25 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=NFC_CE2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
-	/* VIU_DATA5-VIU_DATA9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
-	/* LPC_TSIZ1-LPC_TSIZ2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TS */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO16 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
-	/* GPIO18-GPIO19, GPT7/GPIO7 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO0/GPT0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
-	/* GPIO11, GPIO2, GPIO12, GPIO13 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_DE */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-int checkboard (void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	puts("Board: PDM360NG\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
-	setbits_be32(&im->io_ctrl.io_control_gp,
-		     (1 << 0) |   /* GP_MUX7->GPIO7 */
-		     (1 << 5));	  /* GP_MUX2->GPIO2 */
-
-	/* configure GPIO24 (VIU_CE), output/high */
-	setbits_be32(&im->gpio.gpdir, 0x80);
-	setbits_be32(&im->gpio.gpdat, 0x80);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-struct node_info nodes[] = {
-	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
-	{ "cfi-flash",		MTD_DEV_TYPE_NOR,  },
-};
-#endif
-
-#if defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
- * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
- * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
- * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
- * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
- * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
- * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
- * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
-	0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
-	0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
-	0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
-	0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
-	0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
-	0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
-	0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
-	0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
-	0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
-	0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
-	0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
-	0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
-};
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	u32 val[8];
-	int rc, i = 0;
-
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
-#endif
-
-	/* Fixup NOR FLASH mapping */
-	val[i++] = 0;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = gd->bd->bi_flashstart;
-	val[i++] = gd->bd->bi_flashsize;
-
-	/* Fixup MRAM mapping */
-	val[i++] = 2;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = CONFIG_SYS_MRAM_BASE;
-	val[i++] = CONFIG_SYS_MRAM_SIZE;
-
-	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update localbus ranges, err=%s\n",
-		       fdt_strerror(rc));
-
-	/* Fixup reg property in NOR Flash node */
-	i = 0;
-	val[i++] = 0;			/* always 0 */
-	val[i++] = 0;			/* start at offset 0 */
-	val[i++] = flash_info[0].size;	/* size of Bank 0 */
-
-	/* Second Bank available? */
-	if (flash_info[1].size > 0) {
-		val[i++] = 0;			/* always 0 */
-		val[i++] = flash_info[0].size;	/* offset of Bank 1 */
-		val[i++] = flash_info[1].size;	/* size of Bank 1 */
-	}
-
-	rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update flash reg property, err=%s\n",
-		       fdt_strerror(rc));
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-/*
- * If argument is NULL, set the LCD brightness to the
- * value from "brightness" environment variable. Set
- * the LCD brightness to the value specified by the
- * argument otherwise. Default brightness is zero.
- */
-#define MAX_BRIGHTNESS	99
-static int set_lcd_brightness(char *brightness)
-{
-	struct stdio_dev *cop_port;
-	char *env;
-	char cmd_buf[20];
-	int val = 0;
-	int cs = 0;
-	int len, i;
-
-	if (brightness) {
-		val = simple_strtol(brightness, NULL, 10);
-	} else {
-		env = getenv("brightness");
-		if (env)
-			val = simple_strtol(env, NULL, 10);
-	}
-
-	if (val < 0)
-		val = 0;
-
-	if (val > MAX_BRIGHTNESS)
-		val = MAX_BRIGHTNESS;
-
-	sprintf(cmd_buf, "$SB;%04d;", val);
-
-	len = strlen(cmd_buf);
-	for (i = 1; i <= len; i++)
-		cs += cmd_buf[i];
-
-	cs = (~cs + 1) & 0xff;
-	sprintf(cmd_buf + len, "%02X\n", cs);
-
-	/* IO Coprocessor communication */
-	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
-	if (!cop_port) {
-		printf("Error: Can't open IO Coprocessor port.\n");
-		return -1;
-	}
-
-	debug("%s: cmd: %s", __func__, cmd_buf);
-	write_port(cop_port, cmd_buf);
-	/*
-	 * Wait for transmission and maybe response data
-	 * before closing the port.
-	 */
-	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
-	memset(cmd_buf, 0, sizeof(cmd_buf));
-	len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
-	if (len)
-		printf("Error: %s\n", cmd_buf);
-
-	close_port(4);
-
-	return 0;
-}
-
-static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
-			      int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	return set_lcd_brightness(argv[1]);
-}
-
-U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
-	"set LCD brightness",
-	"<brightness> - set LCD backlight level to <brightness>.\n"
-);
diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig
deleted file mode 100644
index 3a3eab8576..0000000000
--- a/board/phytec/pcm030/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCM030
-
-config SYS_BOARD
-	default "pcm030"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_CONFIG_NAME
-	default "pcm030"
-
-endif
diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS
deleted file mode 100644
index 4e2ab0d64e..0000000000
--- a/board/phytec/pcm030/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PCM030 BOARD
-M:	Jon Smirl <jonsmirl@gmail.com>
-S:	Maintained
-F:	board/phytec/pcm030/
-F:	include/configs/pcm030.h
-F:	configs/pcm030_defconfig
-F:	configs/pcm030_LOWBOOT_defconfig
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
deleted file mode 100644
index 2bb49dc7aa..0000000000
--- a/board/phytec/pcm030/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pcm030.o
diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README
deleted file mode 100644
index 05faab68c8..0000000000
--- a/board/phytec/pcm030/README
+++ /dev/null
@@ -1,42 +0,0 @@
-To build RAMBOOT, replace this section the main Makefile
-
-pcm030_config \
-pcm030_RAMBOOT_config \
-pcm030_LOWBOOT_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
-		{ echo "CONFIG_SYS_TEXT_BASE = 0xFF000000"	>board/phytec/pcm030/config.tmp ; \
-		  echo "... with LOWBOOT configuration" ; \
-		}
-	@[ -z "$(findstring RAMBOOT_,$@)" ] || \
-	       { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
-			config.tmp ; \
-		 echo "... with RAMBOOT configuration" ; \
-		 echo "... remember to make sure that MBAR is already \
-				switched to 0xF0000000 !!!" ; \
-	       }
-	@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
-	@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
-
-Alternative SDRAM settings:
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x715f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-
-/* Settings for XLB = 99 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714b0f00
-#define SDRAM_CONFIG1	0x63611730
-#define SDRAM_CONFIG2	0x47670000
-
-The board ships default with the environment in EEPROM
-Moving the environment to flash can be more reliable
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
deleted file mode 100644
index 47fc7c04bd..0000000000
--- a/board/phytec/pcm030/mt46v32m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * Eric Schumann, Phytec Messtechnik
- * adapted for mt46v32m16-75 DDR-RAM
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x71500F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x47770000
-
-#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
deleted file mode 100644
index bdd980da91..0000000000
--- a/board/phytec/pcm030/pcm030.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#include "mt46v32m16-75.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, (SDRAM_EMODE));
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode,
-		(SDRAM_MODE | 0x04000000));
-#endif
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
-	/* set mode register */
-	out_be32 (&sdram->mode, (SDRAM_MODE));
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | hi_addr_bit));
-
-	/* set CDM clock enable register, set MPC5200B SDRAM bus */
-	/* to reduced driver strength */
-	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make
- *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
- *	work if CONFIG_SYS_SDRAM_BASE
- *	is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-							 /* 256MB at 0x0 */
-	out_be32 (&mm->sdram0, 0x0000001b);
-							 /* disabled */
-	out_be32 (&mm->sdram1, 0x10000000);
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32 (&mm->sdram0,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-							/* disabled */
-		out_be32 (&mm->sdram0, 0);
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: phyCORE-MPC5200B-tiny\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC2_4	0x02000000UL
-
-void init_ide_reset(void)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("init_ide_reset\n");
-
-	/* Configure PSC2_4 as GPIO output for ATA reset */
-	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
-	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
-	/* Deassert reset */
-	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-
-void ide_set_reset(int idereset)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
deleted file mode 100644
index 738dc80551..0000000000
--- a/board/tqc/tqm5200/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CHARON
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "charon"
-
-endif
-
-if TARGET_TQM5200
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM5200"
-
-endif
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
deleted file mode 100644
index 12d143d73f..0000000000
--- a/board/tqc/tqm5200/MAINTAINERS
+++ /dev/null
@@ -1,23 +0,0 @@
-TQM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/tqc/tqm5200/
-F:	include/configs/aev.h
-F:	configs/aev_defconfig
-F:	include/configs/TQM5200.h
-F:	configs/cam5200_defconfig
-F:	configs/cam5200_niosflash_defconfig
-F:	configs/fo300_defconfig
-F:	configs/MiniFAP_defconfig
-F:	configs/TQM5200_defconfig
-F:	configs/TQM5200_B_defconfig
-F:	configs/TQM5200_B_HIGHBOOT_defconfig
-F:	configs/TQM5200_STK100_defconfig
-F:	configs/TQM5200S_defconfig
-F:	configs/TQM5200S_HIGHBOOT_defconfig
-
-CHARON BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	include/configs/charon.h
-F:	configs/charon_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
deleted file mode 100644
index f7c97b72c8..0000000000
--- a/board/tqc/tqm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tqm5200.o cmd_stk52xx.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
deleted file mode 100644
index c3ae5c010b..0000000000
--- a/board/tqc/tqm5200/cam5200_flash.c
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-
-#if 0
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif
-
-#define swap16(x) __swab16(x)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*
- * CAM5200 is a TQM5200B based board. Additionally it also features
- * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
- * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
- * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
- * access to flash chip slightly more complicated as additional byte
- * swapping is necessary within each 16 bit wide flash 'word'.
- *
- * This driver's task is to handle both flash devices: 32 bit TQM5200B
- * flash chip and 16 bit NIOS cpu flash chip. In the below
- * flash_addr_table table we use least significant address bit to mark
- * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
- * specifics of both flashes.
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_32(flash_info_t * info, ulong dest, ulong data);
-static int write_word_16(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
-	int i, k;
-	int size, erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			printf("AMD ");
-			break;
-		case FLASH_MAN_FUJ:
-			printf("FUJITSU ");
-			break;
-		default:
-			printf("Unknown Vendor ");
-			break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_S29GL128N:
-			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_AM320B:
-			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM320T:
-			printf ("29LV320T (32 Mbit, top boot sect)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			break;
-	}
-
-	printf("  Size: %ld KB in %d Sectors\n",
-			info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf("\n   ");
-
-		printf(" %08lX%s%s", info->start[i],
-				erased ? " E" : "  ",
-				info->protect[i] ? "RO " : "   ");
-	}
-	printf("\n");
-	return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-
-	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
-
-	/* bit 0 used for big flash marking */
-	if ((ulong)addr & 0x1)
-		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
-	else
-		return flash_get_size_32(addr, info);
-}
-
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case AMD_ID_MIRROR:
-			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-					addr[14], addr[15]);
-			switch(addr[14]) {
-				case AMD_ID_GL128N_2:
-					if (addr[15] != AMD_ID_GL128N_3) {
-						DEBUGF("Chip: S29GL128N -> unknown\n");
-						info->flash_id = FLASH_UNKNOWN;
-					} else {
-						DEBUGF("Chip: S29GL128N\n");
-						info->flash_id += FLASH_S29GL128N;
-						info->sector_count = 128;
-						info->size = 0x02000000;
-					}
-					break;
-				default:
-					info->flash_id = FLASH_UNKNOWN;
-					return(0);
-			}
-			break;
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00040000);
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_32(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return flash_erase_16(info, s_first, s_last);
-	} else {
-		return flash_erase_32(info, s_first, s_last);
-	}
-}
-
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!", prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_32(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return (0);
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *) cp);
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return write_word_16(info, dest, data);
-	} else {
-		return write_word_32(info, dest, data);
-	}
-}
-
-static int write_word_32(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i, flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return (2);
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-	}
-
-	return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef  CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
-	udelay(1000);
-
-	value = swap16(addr2[0]);
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = swap16(addr2[1]);	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type        */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000a000;
-		info->start[6] = base + 0x0000c000;
-		info->start[7] = base + 0x0000e000;
-
-		for (i = 8; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-	} else {
-		/* set sector offsets for top boot block type           */
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000a000;
-		info->start[i--] = base + info->size - 0x0000c000;
-		info->start[i--] = base + info->size - 0x0000e000;
-
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00010000;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_16(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!",	prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_16(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-static int write_word_16(flash_info_t * info, ulong dest, ulong data)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
-			return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
-
-		dest2[i] = swap16(data2[i]);
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0)
-			continue;
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
-				&flash_info[i]);
-
-		flash_info[i].size = size_b[i];
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-					i+1, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_ADDR_REDUND)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#endif
-#endif
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
-#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
deleted file mode 100644
index a3916ed957..0000000000
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ /dev/null
@@ -1,1228 +0,0 @@
-/*
- * (C) Copyright 2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * STK52XX specific functions
- */
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#if defined(CONFIG_CMD_BSP)
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define DEFAULT_VOL	45
-#define DEFAULT_FREQ	500
-#define DEFAULT_DURATION	200
-#define LEFT		1
-#define RIGHT		2
-#define LEFT_RIGHT	3
-#define BL_OFF		0
-#define BL_ON		1
-
-#define SM501_GPIO_CTRL_LOW		0x00000008UL
-#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_LOW		0x00010000UL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			  unsigned int channel);
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel);
-static void spi_init(void);
-static int spi_transmit(unsigned char data);
-static void pcm1772_write_reg(unsigned char addr, unsigned char data);
-static void set_attenuation(unsigned char attenuation);
-
-static void spi_init(void)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* PSC3 as SPI and GPIOs */
-	gpio->port_config &= 0xFFFFF0FF;
-	gpio->port_config |= 0x00000800;
-	/*
-	 * Its important to use the correct order when initializing the
-	 * registers
-	 */
-	spi->ddr = 0x0F; /* set all SPI pins as output */
-	spi->pdr = 0x08; /* set SS high */
-	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
-	spi->cr2 = 0x00; /* normal operation */
-	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
-}
-
-static int spi_transmit(unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->dr = data;
-	/* wait for SPI transmission completed */
-	while (!(spi->sr & 0x80)) {
-		if (spi->sr & 0x40) {	/* if write collision occurred */
-			int dummy;
-
-			/* do dummy read to clear status register */
-			dummy = spi->dr;
-			printf("SPI write collision: dr=0x%x\n", dummy);
-			return -1;
-		}
-	}
-	return (spi->dr);
-}
-
-static void pcm1772_write_reg(unsigned char addr, unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->pdr = 0x00; /* Set SS low */
-	spi_transmit(addr);
-	spi_transmit(data);
-	/* wait some time to meet MS# hold time of PCM1772 */
-	udelay (1);
-	spi->pdr = 0x08; /* set SS high */
-}
-
-static void set_attenuation(unsigned char attenuation)
-{
-	pcm1772_write_reg(0x01, attenuation); /* left channel */
-	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
-	pcm1772_write_reg(0x02, attenuation); /* right channel */
-	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
-}
-
-void amplifier_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* Do this only once, because of the long time delay */
-	if (!init_done) {
-		/* configure PCM1772 audio format as I2S */
-		pcm1772_write_reg(0x03, 0x01);
-		/* enable audio amplifier */
-		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
-		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
-		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
-		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
-		/*
-		 * wait some time to allow amplifier to recover from shutdown
-		 * mode.
-		 */
-		for(i = 0; i < 350; i++)
-			udelay(1000);
-		/*
-		 * The used amplifier (LM4867) has a so called "pop and click"
-		 * elmination filter. The input signal of the amplifier must
-		 * exceed a certain level once after power up to activate the
-		 * generation of the output signal. This is achieved by
-		 * sending a low frequent (nearly inaudible) sawtooth with a
-		 * sufficient signal level.
-		 */
-		set_attenuation(50);
-		i2s_sawtooth (200, 5, LEFT_RIGHT);
-		init_done = 1;
-	}
-}
-
-static void i2s_init(void)
-{
-	unsigned long i;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
-
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
-						  * 5.617 MHz */
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
-						       * register */
-	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
-	psc->ctur = 0x0F;	/* 16 bit frame width */
-
-	for (i = 0; i < 128; i++)
-		psc->psc_buffer_32 = 0; /* clear tx fifo */
-}
-
-static int i2s_play_wave(unsigned long addr, unsigned long len)
-{
-	unsigned long i;
-	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
-							 * wav header*/
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	/*
-	 * play wave file in memory; bytes/words are be swapped
-	 */
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	for(i = 0;i < (len / 4); i++) {
-		unsigned char swapped[4];
-		unsigned long *p = (unsigned long*)swapped;
-
-		swapped[3] = *wave_file++;
-		swapped[2] = *wave_file++;
-		swapped[1] = *wave_file++;
-		swapped[0] = *wave_file++;
-
-		psc->psc_buffer_32 =  *p;
-
-		while (psc->tfnum > 400) {
-			if(ctrlc())
-				return 0;
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	return 0;
-}
-
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sawtooth. Start with middle level up to highest level. Then
-	 * go to lowest level and back to middle level.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			 unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sqarewave. Start with high level, duty cycle 1:1.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x7FFF;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x8000;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long reg, val, duration;
-	char *tmp;
-	unsigned int freq, channel;
-	unsigned char volume;
-	int rcode = 1;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	switch (argc) {
-	case 0:
-	case 1:
-		return cmd_usage(cmdtp);
-	case 2:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-
-		return cmd_usage(cmdtp);
-	case 3:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	case 4:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						LEFT_RIGHT);
-			return rcode;
-		} else if (strcmp(argv[1],"pcm1772") == 0) {
-			reg = simple_strtoul(argv[2], NULL, 10);
-			val = simple_strtoul(argv[3], NULL, 10);
-			printf("Set PCM1772 %lu. %lu\n", reg, val);
-			pcm1772_write_reg((uchar)reg, (uchar)val);
-			return 0;
-		}
-		return cmd_usage(cmdtp);
-	case 5:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      channel);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						channel);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	}
-	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long length, addr;
-	unsigned char volume;
-	int rcode = 1;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-
-	case 3:
-		length = simple_strtoul(argv[2], NULL, 16);
-		addr = simple_strtoul(argv[1], NULL, 16);
-		break;
-
-	case 2:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		addr = simple_strtoul(argv[1], NULL, 16);
-
-	case 1:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		if ((tmp = getenv ("loadaddr")) != NULL) {
-			addr = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No loadaddr provided\n");
-			return 1;
-		}
-		break;
-
-	default:
-		printf("Usage:\nwav <addr> <length[s]\n");
-		return 1;
-		break;
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Play wave file at %lX with length %lX\n", addr, length);
-	rcode = i2s_play_wave(addr, length);
-
-	return rcode;
-}
-
-static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned char volume;
-	unsigned int channel;
-	int rcode;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-	case 0:
-	case 1:
-		channel = LEFT_RIGHT;
-		break;
-	case 2:
-		if (strncmp(argv[1],"l",1) == 0)
-			channel = LEFT;
-		else if (strncmp(argv[1],"r",1) == 0)
-			channel = RIGHT;
-		else
-			channel = LEFT_RIGHT;
-		break;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Beep on ");
-	if (channel == LEFT)
-		printf ("left ");
-	else if (channel == RIGHT)
-		printf ("right ");
-	else
-		printf ("left and right ");
-	printf ("channel\n");
-
-	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
-
-	return rcode;
-}
-#endif
-
-#if defined(CONFIG_STK52XX)
-void led_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	/* configure PSC3 for SPI and GPIO */
-	gpio->port_config &= ~(0x00000F00);
-	gpio->port_config |=   0x00000800;
-
-	gpio->simple_gpioe &= ~(0x00000F00);
-	gpio->simple_gpioe |=   0x00000F00;
-
-	gpio->simple_ddr &= ~(0x00000F00);
-	gpio->simple_ddr |=   0x00000F00;
-
-	/* configure timer 4-7 for simple GPIO output */
-	gpt->gpt4.emsr |=  0x00000024;
-	gpt->gpt5.emsr |=  0x00000024;
-	gpt->gpt6.emsr |=  0x00000024;
-	gpt->gpt7.emsr |=  0x00000024;
-
-#ifndef CONFIG_TQM5200S
-	/* enable SM501 GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-
-	/* configure SM501 gpio pins 24-27 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
-
-	/* configure SM501 gpio pins 48-51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
-#endif /* !CONFIG_TQM5200S */
-}
-
-/*
- * return 1 if led number unknown
- * return 0 else
- */
-int do_led(char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 0:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 8);
-		} else {
-			gpio->simple_dvo &= ~(1 << 8);
-		}
-		break;
-
-	case 1:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 9);
-		} else {
-			gpio->simple_dvo &= ~(1 << 9);
-		}
-		break;
-
-	case 2:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 10);
-		} else {
-			gpio->simple_dvo &= ~(1 << 10);
-		}
-		break;
-
-	case 3:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 11);
-		} else {
-			gpio->simple_dvo &= ~(1 << 11);
-		}
-		break;
-
-	case 4:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt4.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt4.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 5:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt5.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt5.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 6:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt6.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt6.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 7:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt7.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt7.emsr &=  ~(1 << 4);
-		}
-		break;
-#ifndef CONFIG_TQM5200S
-	case 24:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 24);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 24);
-		}
-		break;
-
-	case 25:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 25);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 25);
-		}
-		break;
-
-	case 26:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 26);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 26);
-		}
-		break;
-
-	case 27:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 27);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 27);
-		}
-		break;
-
-	case 48:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 16);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 16);
-		}
-		break;
-
-	case 49:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 17);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 17);
-		}
-		break;
-
-	case 50:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 18);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 18);
-		}
-		break;
-
-	case 51:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 19);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 19);
-		}
-		break;
-#endif /* !CONFIG_TQM5200S */
-	default:
-		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
-		return 1;
-	}
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-/*
- * return 1 on CAN initialization failure
- * return 0 if no failure
- */
-int can_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* GPIO configuration of the CAN pins is done in TQM5200.h */
-
-	if (!init_done) {
-		/* init CAN 1 */
-		can1->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can1->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can1->canctl1 & 0x02)) {
-			udelay(10);
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 initialize error, "
-				"can not enter sleep mode!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		}
-		i = 0;
-		can1->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can1->canctl1 & 0x01)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can1->canctl1 = 0x80;
-		can1->canctl1 |= 0x40;
-		can1->canbtr0 = 0x0F;
-		can1->canbtr1 = 0x7F;
-		can1->canidac &= ~(0x30);
-		can1->canidar1 = 0x00;
-		can1->canidar3 = 0x00;
-		can1->canidar5 = 0x00;
-		can1->canidar7 = 0x00;
-		can1->canidmr0 = 0xFF;
-		can1->canidmr1 = 0xFF;
-		can1->canidmr2 = 0xFF;
-		can1->canidmr3 = 0xFF;
-		can1->canidmr4 = 0xFF;
-		can1->canidmr5 = 0xFF;
-		can1->canidmr6 = 0xFF;
-		can1->canidmr7 = 0xFF;
-
-		i = 0;
-		can1->canctl0 &= ~(0x01);	/* leave init mode */
-		can1->canctl0 &= ~(0x02);
-		/* wait until init and sleep mode left */
-		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-
-		/* init CAN 2 */
-		can2->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can2->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can2->canctl1 & 0x02))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		i = 0;
-		can2->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can2->canctl1 & 0x01))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can2->canctl1 = 0x80;
-		can2->canctl1 |= 0x40;
-		can2->canbtr0 = 0x0F;
-		can2->canbtr1 = 0x7F;
-		can2->canidac &= ~(0x30);
-		can2->canidar1 = 0x00;
-		can2->canidar3 = 0x00;
-		can2->canidar5 = 0x00;
-		can2->canidar7 = 0x00;
-		can2->canidmr0 = 0xFF;
-		can2->canidmr1 = 0xFF;
-		can2->canidmr2 = 0xFF;
-		can2->canidmr3 = 0xFF;
-		can2->canidmr4 = 0xFF;
-		can2->canidmr5 = 0xFF;
-		can2->canidmr6 = 0xFF;
-		can2->canidmr7 = 0xFF;
-		can2->canctl0 &= ~(0x01);	/* leave init mode */
-		can2->canctl0 &= ~(0x02);
-
-		i = 0;
-		/* wait until init mode left */
-		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		init_done = 1;
-	}
-	return 0;
-}
-
-/*
- * return 1 on CAN failure
- * return 0 if no failure
- */
-int do_can(char * const argv[])
-{
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* send a message on CAN1 */
-	can1->cantbsel = 0x01;
-	can1->cantxfg.idr[0] = 0x55;
-	can1->cantxfg.idr[1] = 0x00;
-	can1->cantxfg.idr[1] &= ~0x8;
-	can1->cantxfg.idr[1] &= ~0x10;
-	can1->cantxfg.dsr[0] = 0xCC;
-	can1->cantxfg.dlr = 1;
-	can1->cantxfg.tbpr = 0;
-	can1->cantflg = 0x01;
-
-	i = 0;
-	while ((can1->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 send timeout, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can2->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can2->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN2 receive error, "
-			 "data mismatch!\n",
-			__FUNCTION__);
-		return 1;
-	}
-
-	/* send a message on CAN2 */
-	can2->cantbsel = 0x01;
-	can2->cantxfg.idr[0] = 0x55;
-	can2->cantxfg.idr[1] = 0x00;
-	can2->cantxfg.idr[1] &= ~0x8;
-	can2->cantxfg.idr[1] &= ~0x10;
-	can2->cantxfg.dsr[0] = 0xCC;
-	can2->cantxfg.dlr = 1;
-	can2->cantxfg.tbpr = 0;
-	can2->cantflg = 0x01;
-
-	i = 0;
-	while ((can2->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 send error, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can1->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can1->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN1 receive error 0x%02x\n",
-			__FUNCTION__, (can1->canrxfg.dsr[0]));
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * return 1 if rs232 port unknown
- * return 2 on txd/rxd failure (only rs232 2)
- * return 3 on rts/cts failure
- * return 0 if no failure
- */
-int do_rs232(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		break;
-
-	case 2:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |=   (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |=   (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000F00;
-		break;
-
-	default:
-		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-
-	return error_status;
-}
-
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-static void sm501_backlight (unsigned int state)
-{
-	if (state == BL_ON) {
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
-			(1 << 26) | (1 << 27);
-	} else if (state == BL_OFF)
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
-			~((1 << 26) | (1 << 27));
-}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-
-int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-#if defined(CONFIG_STK52XX)
-	led_init();
-#endif
-	can_init();
-
-	switch (argc) {
-
-	case 0:
-	case 1:
-		break;
-
-	case 2:
-		if (strncmp (argv[1], "can", 3) == 0) {
-			rcode = do_can (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-		}
-		break;
-
-	case 3:
-		if (strncmp (argv[1], "rs232", 3) == 0) {
-			rcode = do_rs232 (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-		} else if (strncmp (argv[1], "backlight", 4) == 0) {
-			if (strncmp (argv[2], "on", 2) == 0) {
-				sm501_backlight (BL_ON);
-				return 0;
-			}
-			else if (strncmp (argv[2], "off", 3) == 0) {
-				sm501_backlight (BL_OFF);
-				return 0;
-			}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-		}
-		break;
-
-#if defined(CONFIG_STK52XX)
-	case 4:
-		if (strcmp (argv[1], "led") == 0) {
-			return (do_led (argv));
-		}
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-
-U_BOOT_CMD(
-	sound ,    5,    1,     cmd_sound,
-	"Sound sub-system",
-	"saw [duration] [freq] [channel]\n"
-	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"sound square [duration] [freq] [channel]\n"
-	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"pcm1772 reg val"
-);
-
-U_BOOT_CMD(
-	wav ,    3,    1,     cmd_wav,
-	"play wav file",
-	"[addr] [bytes]\n"
-	"    - play wav file at address 'addr' with length 'bytes'"
-);
-
-U_BOOT_CMD(
-	beep ,    2,    1,     cmd_beep,
-	"play short beep",
-	"[channel]\n"
-	"    - play short beep on \"l\"eft or \"r\"ight channel"
-);
-#endif /* CONFIG_STK52XX  || CONFIG_FO300 */
-
-#if defined(CONFIG_STK52XX)
-U_BOOT_CMD(
-	fkt ,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"led number on/off\n"
-	"     - 'number's like printed on STK52XX board\n"
-	"fkt can\n"
-	"     - loopback plug for X83 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X2 required"
-#ifndef CONFIG_TQM5200S
-	"\n"
-	"fkt backlight on/off\n"
-	"     - switch backlight on or off"
-#endif /* !CONFIG_TQM5200S */
-);
-#elif defined(CONFIG_FO300)
-U_BOOT_CMD(
-	fkt ,	3,	1,	cmd_fkt,
-	"Function test routines",
-	"fkt can\n"
-	"     - loopback plug for X16/X29 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X21/X22 required"
-);
-#endif
-#endif
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
deleted file mode 100644
index 3d9979664f..0000000000
--- a/board/tqc/tqm5200/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
-#define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
deleted file mode 100644
index cb99afdb90..0000000000
--- a/board/tqc/tqm5200/tqm5200.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-#include <video.h>
-
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-#endif
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
-    defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- *
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- *     00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
- *     10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
- *     20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
- *     30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
- *     40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
- *     50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
- *     60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
- *     70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
-};
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced dram_init does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-#if defined(CONFIG_TQM5200_B)
-	gd->ram_size = dramsize + dramsize2;
-#else
-	gd->ram_size = dramsize;
-#endif /* CONFIG_TQM5200_B */
-
-	return 0;
-}
-
-int checkboard (void)
-{
-#if defined(CONFIG_TQM5200S)
-# define MODULE_NAME	"TQM5200S"
-#else
-# define MODULE_NAME	"TQM5200"
-#endif
-
-#if defined(CONFIG_STK52XX)
-# define CARRIER_NAME	"STK52xx"
-#elif defined(CONFIG_CAM5200)
-# define CARRIER_NAME	"CAM5200"
-#elif defined(CONFIG_FO300)
-# define CARRIER_NAME	"FO300"
-#elif defined(CONFIG_CHARON)
-# define CARRIER_NAME	"CHARON"
-#else
-# error "UNKNOWN"
-#endif
-
-	puts (	"Board: " MODULE_NAME " (TQ-Components GmbH)\n"
-		"       on a " CARRIER_NAME " carrier board\n");
-
-	return 0;
-}
-
-#undef MODULE_NAME
-#undef CARRIER_NAME
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-
-#if defined (CONFIG_MINIFAP)
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_51			0x00080000UL
-#endif /* CONFIG MINIFAP */
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-#if defined (CONFIG_MINIFAP)
-	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
-
-	/* enable GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	/* configure GPIO51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
-		SM501_GPIO_51;
-#else
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-
-	/* by default the ATA reset is de-asserted */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-#endif
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-#if defined (CONFIG_MINIFAP)
-	if (idereset) {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-			~SM501_GPIO_51;
-	} else {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-			SM501_GPIO_51;
-	}
-#else
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-#endif
-}
-#endif
-
-#ifdef CONFIG_POST
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-#ifdef CONFIG_STK52XX
-	struct mpc5xxx_gpio *gpio;
-
-	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_0 through PSC6_3 as GPIO.
-	 */
-	gpio->port_config &= ~(0x00700000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	gpio->simple_gpioe |= 0x20000000;
-
-	/* Configure GPIO_IRDA_1 as input */
-	gpio->simple_ddr &= ~(0x20000000);
-
-	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
-#else
-	return 0;
-#endif
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-
-	extern int usb_cpu_init(void);
-
-#ifdef CONFIG_PS2MULT
-	ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-
-	return (0);
-}
-#endif
-
-#ifdef CONFIG_FO300
-int silent_boot (void)
-{
-	vu_long timer3_status;
-
-	/* Configure GPT3 as GPIO input */
-	*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
-
-	/* Read in TIMER_3 pin status */
-	timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
-
-#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
-	/* Force silent console mode if S1 switch
-	 * is in closed position (TIMER_3 pin status is LOW). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
-		return 1;
-#else
-	/* Force silent console mode if S1 switch
-	 * is in open position (TIMER_3 pin status is HIGH). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
-		return 1;
-#endif
-
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	if (silent_boot())
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-#endif	/* CONFIG_FO300 */
-
-#if defined(CONFIG_CHARON)
-#include <i2c.h>
-#include <asm/io.h>
-
-/* The TFP410 registers */
-#define TFP410_REG_VEN_ID_L 0x00
-#define TFP410_REG_VEN_ID_H 0x01
-#define TFP410_REG_DEV_ID_L 0x02
-#define TFP410_REG_DEV_ID_H 0x03
-#define TFP410_REG_REV_ID 0x04
-
-#define TFP410_REG_CTL_1_MODE 0x08
-#define TFP410_REG_CTL_2_MODE 0x09
-#define TFP410_REG_CTL_3_MODE 0x0A
-
-#define TFP410_REG_CFG 0x0B
-
-#define TFP410_REG_DE_DLY 0x32
-#define TFP410_REG_DE_CTL 0x33
-#define TFP410_REG_DE_TOP 0x34
-#define TFP410_REG_DE_CNT_L 0x36
-#define TFP410_REG_DE_CNT_H 0x37
-#define TFP410_REG_DE_LIN_L 0x38
-#define TFP410_REG_DE_LIN_H 0x39
-
-#define TFP410_REG_H_RES_L 0x3A
-#define TFP410_REG_H_RES_H 0x3B
-#define TFP410_REG_V_RES_L 0x3C
-#define TFP410_REG_V_RES_H 0x3D
-
-static int tfp410_read_reg(int reg, uchar *buf)
-{
-	puts("Error reading the chip.\n");
-	return -ENOSYS;
-}
-
-static int tfp410_write_reg(int reg, uchar buf)
-{
-	puts("Error writing the chip.\n");
-	return -ENOSYS;
-}
-
-typedef struct _tfp410_config {
-	int	reg;
-	uchar	val;
-}TFP410_CONFIG;
-
-static TFP410_CONFIG tfp410_configtbl[] = {
-	{TFP410_REG_CTL_1_MODE, 0x37},
-	{TFP410_REG_CTL_2_MODE, 0x20},
-	{TFP410_REG_CTL_3_MODE, 0x80},
-	{TFP410_REG_DE_DLY, 0x90},
-	{TFP410_REG_DE_CTL, 0x00},
-	{TFP410_REG_DE_TOP, 0x23},
-	{TFP410_REG_DE_CNT_H, 0x02},
-	{TFP410_REG_DE_CNT_L, 0x80},
-	{TFP410_REG_DE_LIN_H, 0x01},
-	{TFP410_REG_DE_LIN_L, 0xe0},
-	{-1, 0},
-};
-
-static int charon_last_stage_init(void)
-{
-	volatile struct mpc5xxx_lpb *lpb =
-		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
-	uchar	buf;
-	int	i = 0;
-
-	/* check version */
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
-		return -1;
-	if (!(buf & 0x04))
-		return -1;
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
-		return -1;
-	if (!(buf & 0x10))
-		return -1;
-	/* OK, now init the chip */
-	while (tfp410_configtbl[i].reg != -1) {
-		int ret;
-
-		ret = tfp410_write_reg(tfp410_configtbl[i].reg,
-				tfp410_configtbl[i].val);
-		if (ret != 0)
-			return -1;
-		i++;
-	}
-	printf("TFP410 initialized.\n");
-
-	/* set deadcycle for cs3 to 0 */
-	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
-	return 0;
-}
-#endif
-
-int last_stage_init (void)
-{
-	/*
-	 * auto scan for really existing devices and re-set chip select
-	 * configuration.
-	 */
-	u16 save, tmp;
-	int restore;
-
-	/*
-	 * Check for SRAM and SRAM size
-	 */
-
-	/* save original SRAM content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
-	restore = 1;
-
-	/* write test pattern to SRAM */
-	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in SRAM detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
-		/* no SRAM at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
-		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
-		/* make sure that we access a mirrored address */
-		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
-		__asm__ volatile ("sync");
-		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
-			/* SRAM size = 512 kByte */
-			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
-								0x80000);
-			__asm__ volatile ("sync");
-			puts ("SRAM:  512 kB\n");
-		}
-		else
-			puts ("!! possible error in SRAM detection\n");
-	} else {
-		puts ("SRAM:  1 MB\n");
-	}
-	/* restore origianl SRAM content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifndef CONFIG_TQM5200S	/* The TQM5200S has no SM501 grafic controller */
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
-		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else {
-		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
-	}
-	/* restore origianl FB content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifdef CONFIG_FO300
-	if (silent_boot()) {
-		setenv("bootdelay", "0");
-		disable_ctrlc(1);
-	}
-#endif
-#endif /* !CONFIG_TQM5200S */
-
-#if defined(CONFIG_CHARON)
-	charon_last_stage_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_VIDEO_SM501
-
-#ifdef CONFIG_FO300
-#define DISPLAY_WIDTH   800
-#else
-#define DISPLAY_WIDTH   640
-#endif
-#define DISPLAY_HEIGHT  480
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#error CONFIG_VIDEO_SM501_16BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-#ifdef CONFIG_VIDEO_SM501_32BPP
-static const SMI_REGS init_regs [] =
-{
-#if 0 /* CRT only */
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x10090a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x10090a01},
-	{0x00054, 0x0},
-	{0x80200, 0x00010000},
-	{0x80204, 0x0},
-	{0x80208, 0x0A000A00},
-	{0x8020C, 0x02fa027f},
-	{0x80210, 0x004a028b},
-	{0x80214, 0x020c01df},
-	{0x80218, 0x000201e9},
-	{0x80200, 0x00013306},
-#else  /* panel + CRT */
-#ifdef CONFIG_FO300
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x301a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0C800C80},
-	{0x80014, 0x03200000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00320},
-	{0x80024, 0x042a031f},
-	{0x80028, 0x0086034a},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201ea},
-	{0x80200, 0x00010000},
-#else
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x091a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0a000a00},
-	{0x80014, 0x02800000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00280},
-	{0x80024, 0x02fa027f},
-	{0x80028, 0x004a028b},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201e9},
-	{0x80200, 0x00010000},
-#endif /* #ifdef CONFIG_FO300 */
-#endif
-	{0, 0}
-};
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1) {
-	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
-	defined(CONFIG_STK52XX)
-	} else if (line_number == 2) {
-#if defined (CONFIG_CHARON)
-		strcpy (info, "        on a CHARON carrier board");
-#endif
-#if defined (CONFIG_STK52XX)
-		strcpy (info, "        on a STK52xx carrier board");
-#endif
-#if defined (CONFIG_FO300)
-		strcpy (info, "        on a FO300 carrier board");
-#endif
-#endif
-	}
-	else {
-		info [0] = '\0';
-	}
-}
-#endif
-
-/*
- * Returns SM501 register base address. First thing called in the
- * driver. Checks if SM501 is physically present.
- */
-unsigned int board_video_init (void)
-{
-	u16 save, tmp;
-	int restore, ret;
-
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller found */
-		restore = 0;
-		ret = 0;
-	} else {
-		ret = SM501_MMIO_BASE;
-	}
-
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-	return ret;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
-	return SM501_FB_BASE;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
-	return init_regs;
-}
-
-int board_get_width (void)
-{
-	return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
-	return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "smi,sm501", edid_buf);
-#endif
-
-	return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_RESET_PHY_R)
-#include <miiphy.h>
-
-void reset_phy(void)
-{
-	/* init Micrel KSZ8993 PHY */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig
deleted file mode 100644
index 653bfc1c3b..0000000000
--- a/board/v38b/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_V38B
-
-config SYS_BOARD
-	default "v38b"
-
-config SYS_CONFIG_NAME
-	default "v38b"
-
-endif
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
deleted file mode 100644
index d1a6ae6b2f..0000000000
--- a/board/v38b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-V38B BOARD
-#M:	-
-S:	Maintained
-F:	board/v38b/
-F:	include/configs/v38b.h
-F:	configs/v38b_defconfig
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
deleted file mode 100644
index a20a5ef0e9..0000000000
--- a/board/v38b/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= v38b.o ethaddr.o
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
deleted file mode 100644
index 982998fadc..0000000000
--- a/board/v38b/ethaddr.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* For the V38B board the pin is GPIO_PSC_6 */
-#define GPIO_PIN	GPIO_PSC6_0
-
-#define NO_ERROR	0
-#define ERR_NO_NUMBER	1
-#define ERR_BAD_NUMBER	2
-
-static int is_high(void);
-static int check_device(void);
-static void io_out(int value);
-static void io_input(void);
-static void io_output(void);
-static void init_gpio(void);
-static void read_byte(unsigned char *data);
-static void write_byte(unsigned char command);
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr);
-void board_get_enetaddr(uchar *enetaddr);
-
-
-static int is_high()
-{
-	return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
-}
-
-static void io_out(int value)
-{
-	if (value)
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
-	else
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
-}
-
-static void io_input()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
-	udelay(3);	/* allow input to settle */
-}
-
-static void io_output()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
-}
-
-static void init_gpio()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
-}
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr)
-{
-#define NBYTES 28
-	unsigned char crcval, i;
-	unsigned char buf[NBYTES];
-
-	*perr = 0;
-	crcval = 0;
-
-	for (i = 0; i < NBYTES; i++)
-		buf[i] = 0;
-
-	if (!check_device())
-		*perr = ERR_NO_NUMBER;
-	else {
-		*perr = NO_ERROR;
-		write_byte(0xCC);		/* skip ROM (0xCC) */
-		write_byte(0xF0);		/* Read memory command 0xF0 */
-		write_byte(0x00);		/* Address TA1=0, TA2=0 */
-		write_byte(0x00);
-		read_byte(&crcval);		/* Read CRC of address and command */
-
-		for (i = 0; i < NBYTES; i++)
-			read_byte(&buf[i]);
-	}
-	if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
-		*perr = ERR_BAD_NUMBER;
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = 0xFF;
-		psernum[4] = 0xFF;
-		psernum[5] = 0xFF;
-	} else {
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = buf[7];
-		psernum[4] = buf[6];
-		psernum[5] = buf[5];
-	}
-}
-
-static int check_device()
-{
-	int found;
-
-	io_output();
-	io_out(0);
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	io_input();
-	udelay(60);
-
-	found = (is_high() == 0) ? 1 : 0;
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	return found;
-}
-
-static void write_byte(unsigned char command)
-{
-	char i;
-
-	for (i = 0; i < 8; i++) {
-		/* 1 us to 15 us low pulse starts bit slot */
-		/* Start with high pulse for 3 us */
-		io_input();
-		udelay(3);
-
-		io_out(0);
-		io_output();
-		udelay(3);
-
-		if (command & 0x01) {
-			/* 60 us high for 1-bit */
-			io_input();
-			udelay(60);
-		} else
-			/* 60 us low for 0-bit */
-			udelay(60);
-		/*  Leave pin as input */
-		io_input();
-
-		command = command >> 1;
-	}
-}
-
-static void read_byte(unsigned char *data)
-{
-	unsigned char i, rdat = 0;
-
-	for (i = 0; i < 8; i++) {
-		/* read one bit from one-wire device */
-
-		/* 1 - 15 us low starts bit slot */
-		io_out(0);
-		io_output();
-		udelay(0);
-
-		/* allow line to be pulled high */
-		io_input();
-
-		/* delay 10 us */
-		udelay(10);
-
-		/* now sample input status */
-		if (is_high())
-			rdat = (rdat >> 1) | 0x80;
-		else
-			rdat = rdat >> 1;
-
-		udelay(60);	/* at least 60 us */
-	}
-	/* copy the return value */
-	*data = rdat;
-}
-
-void board_get_enetaddr(uchar *enetaddr)
-{
-	unsigned char sn[6], err = NO_ERROR;
-
-	init_gpio();
-
-	read_2501_memory(sn, &err);
-
-	if (err == NO_ERROR) {
-		sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
-				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
-		printf("MAC address: %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	} else {
-		sprintf((char *)enetaddr, "00:01:02:03:04:05");
-		printf("Error reading MAC address.\n");
-		printf("Setting default to %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	}
-}
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
deleted file mode 100644
index e680b7b8ff..0000000000
--- a/board/v38b/v38b.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-int dram_init(void)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else
-		dramsize2 = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	gd->ram_size = dramsize + dramsize2;
-
-	return 0;
-}
-
-
-int checkboard (void)
-{
-	puts("Board: MarelV38B\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
-	/*
-	 * Enable and configure the direction (output) of PSC3_9 - watchdog
-	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
-	 * Manual.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
-#endif /* CONFIG_HW_WATCHDOG */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for the
-	 * detection process.  Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/*
-	 * Enable GPIO_WKUP_7 to "read the status of the actual power
-	 * situation". Default direction is input, so no need to set it
-	 * explicitly.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
-	return 0;
-}
-
-extern void board_get_enetaddr(uchar *enetaddr);
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-}
-#endif
-
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	/*
-	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
-	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
-}
-#endif /* CONFIG_HW_WATCHDOG */