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| author | Neal Frager <neal.frager@amd.com> | 2022-05-10 16:18:42 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-05-18 13:17:18 +0200 |
| commit | 80b8bbbf98fcb062d7bbc7bff10ef51086d3c422 (patch) | |
| tree | 08261167120c1921566b4701bf369db326b8399c /board/xilinx | |
| parent | 155353234ec2259efae88c9973f81a53a2b9afb5 (diff) | |
| download | u-boot-80b8bbbf98fcb062d7bbc7bff10ef51086d3c422.tar.gz u-boot-80b8bbbf98fcb062d7bbc7bff10ef51086d3c422.tar.bz2 u-boot-80b8bbbf98fcb062d7bbc7bff10ef51086d3c422.zip | |
arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.
The Linux DP driver expects the DP to be using the following PLL config:
- DP video PLL should use the VPLL (0x0)
- DP audio PLL should use the RPLL (0x3)
Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com
Diffstat (limited to 'board/xilinx')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c index 2ac4e035d8..3dc9bf8f3a 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); |