summaryrefslogtreecommitdiff
path: root/board/xilinx/zynq
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2021-02-23 10:45:55 -0500
committerTom Rini <trini@konsulko.com>2021-02-23 10:45:55 -0500
commitcbe607b920bc0827d8fe379ed4f5ae4e2058513e (patch)
treeb8cdbb8856766675f37bb92f27ab9c662fa647f9 /board/xilinx/zynq
parent8f7a16aac36c2a38956bd04b53cb7b94b7a70180 (diff)
parentd9aa19efa8a6c20d51b7884de0a7f8dae3f835d2 (diff)
downloadu-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.tar.gz
u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.tar.bz2
u-boot-cbe607b920bc0827d8fe379ed4f5ae4e2058513e.zip
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
Diffstat (limited to 'board/xilinx/zynq')
-rw-r--r--board/xilinx/zynq/board.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 49ff3f0dc0..7533dddb9b 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -25,6 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ printf("Silicon version:\t%d\n", zynq_get_silicon_version());
+
return 0;
}