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| author | Marek Vasut <marek.vasut@gmail.com> | 2017-10-04 03:03:50 +0200 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2017-10-10 08:22:47 +0900 |
| commit | 3219c77e58a8b6d272a40d87b06361f1e7882712 (patch) | |
| tree | 65cd997d8c06c898b0993878add4c913df6b04f9 /board/renesas/ulcb | |
| parent | fd107e32ee18e239626b2fb6103413277bb336a8 (diff) | |
| download | u-boot-3219c77e58a8b6d272a40d87b06361f1e7882712.tar.gz u-boot-3219c77e58a8b6d272a40d87b06361f1e7882712.tar.bz2 u-boot-3219c77e58a8b6d272a40d87b06361f1e7882712.zip | |
ARM: rmobile: Fixup ULCB CPLD support after PFC rework
The ULCB CPLD support was not updated during the PFC table rework,
fix up the GPIO numbers until the CPLD support is rewritten to a
proper DM capable and DT probing driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/ulcb')
| -rw-r--r-- | board/renesas/ulcb/cpld.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c index f9384b09ef..a1fecf18e5 100644 --- a/board/renesas/ulcb/cpld.c +++ b/board/renesas/ulcb/cpld.c @@ -12,10 +12,10 @@ #include <asm/io.h> #include <asm/gpio.h> -#define SCLK GPIO_GP_6_8 -#define SSTBZ GPIO_GP_2_3 -#define MOSI GPIO_GP_6_7 -#define MISO GPIO_GP_6_10 +#define SCLK (192 + 8) /* GPIO6 8 */ +#define SSTBZ (64 + 3) /* GPIO2 3 */ +#define MOSI (192 + 7) /* GPIO6 8 */ +#define MISO (192 + 10) /* GPIO6 10 */ #define CPLD_ADDR_MODE 0x00 /* RW */ #define CPLD_ADDR_MUX 0x02 /* RW */ |