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| author | Wolfgang Denk <wd@denx.de> | 2008-01-08 17:15:18 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-01-08 17:15:18 +0100 |
| commit | 74ac5facb988fc488a707db228b177ead63a6541 (patch) | |
| tree | ca69b5c618952221c1078fb1742eb07202eb44f4 /board/inka4x0/hyb25d512160bf-5.h | |
| parent | 207f83f102b07cb186a2da0678c51ed954f1b431 (diff) | |
| parent | 5e71c51d74c963d3174060c078dcacf13bdd02ef (diff) | |
| download | u-boot-74ac5facb988fc488a707db228b177ead63a6541.tar.gz u-boot-74ac5facb988fc488a707db228b177ead63a6541.tar.bz2 u-boot-74ac5facb988fc488a707db228b177ead63a6541.zip | |
Merge branch 'inka4x0-ng' of /home/m8/git/u-boot/
Diffstat (limited to 'board/inka4x0/hyb25d512160bf-5.h')
| -rw-r--r-- | board/inka4x0/hyb25d512160bf-5.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h new file mode 100644 index 0000000000..7eb1f50158 --- /dev/null +++ b/board/inka4x0/hyb25d512160bf-5.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2007 Semihalf + * Written by Marian Balakowicz <m8@semihalf.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONFIG1 0x73711930 +#define SDRAM_CONFIG2 0x46770000 +#define SDRAM_TAPDELAY 0x10000000 |