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authorTom Rini <trini@konsulko.com>2022-07-23 13:04:57 -0400
committerTom Rini <trini@konsulko.com>2022-08-04 16:18:47 -0400
commit90df583c64fac80bb5f8f6ed48c20a0d75128cde (patch)
tree19a9533fc923ecdbe932aa83afa73d267ada6d6b /board/imgtec
parent9a56ab96aa3206001c89151eb2755479f708f084 (diff)
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malta: Switch to using CONFIG_SYS_SDRAM_SIZE
This is the only platform defining and using CONFIG_SYS_MEM_SIZE, switch to using CONFIG_SYS_SDRAM_SIZE for consistency. Cc: Paul Burton <paul.burton@mips.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/imgtec')
-rw-r--r--board/imgtec/malta/lowlevel_init.S4
-rw-r--r--board/imgtec/malta/malta.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index ecb4424fd9..bed24972f7 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -118,7 +118,7 @@ _msc01:
/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
- li t2, -CONFIG_SYS_MEM_SIZE
+ li t2, -CONFIG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@ _msc01:
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_MEM_SIZE
+ li t1, -CONFIG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index d2e2e4ae20..9853a0ba82 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void)
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_MEM_SIZE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}