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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-08-14 08:43:07 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:14 -0700 |
| commit | 9e0081d573442e7234355f0a043218d15df03933 (patch) | |
| tree | bc508d9fa9b248d70cac2ed736d834d22f5e0e3b /board/hale | |
| parent | b809b3ac13e1016b2be937bd4511973f90982ad2 (diff) | |
| download | u-boot-9e0081d573442e7234355f0a043218d15df03933.tar.gz u-boot-9e0081d573442e7234355f0a043218d15df03933.tar.bz2 u-boot-9e0081d573442e7234355f0a043218d15df03933.zip | |
mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/hale')
| -rw-r--r-- | board/hale/tt01/tt01.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c index 02e75edb40..143fcefedf 100644 --- a/board/hale/tt01/tt01.c +++ b/board/hale/tt01/tt01.c @@ -52,7 +52,7 @@ static void board_setup_clocks(void) writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); /* Set up clock to 532MHz */ - writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0), &ccm->pdr0); |