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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-02-05 11:28:26 +0900 |
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committer | Tom Rini <trini@ti.com> | 2014-02-19 11:10:05 -0500 |
commit | 5ab502cb8900aee483dfba28700640672e0b060e (patch) | |
tree | 55cdefd0d3db1f47bbe0292cfbd571eed0dd76b1 /board/chromebook-x86 | |
parent | 6ab6b2afa091dbceb37719b8a81637a00834be19 (diff) | |
download | u-boot-5ab502cb8900aee483dfba28700640672e0b060e.tar.gz u-boot-5ab502cb8900aee483dfba28700640672e0b060e.tar.bz2 u-boot-5ab502cb8900aee483dfba28700640672e0b060e.zip |
dts: move device tree sources to arch/$(ARCH)/dts/
Unlike Linux Kernel, U-Boot historically had *.dts files under
board/$(VENDOR)/dts/ and *.dtsi files under arch/$(ARCH)/dts/.
I think arch/$(ARCH)/dts dicretory is a better location
to store both *.dts and *.dtsi files.
For example, before this commit, board/xilinx/dts directory
had both Microblaze dts (microblaze-generic.dts) and
ARM dts (zynq-*.dts), which are totally unrelated.
This commit moves *.dts to arch/$(ARCH)/dts/ directories,
allowing us to describe nicely mutiple DTBs generation in the next commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'board/chromebook-x86')
-rw-r--r-- | board/chromebook-x86/dts/alex.dts | 24 | ||||
-rw-r--r-- | board/chromebook-x86/dts/link.dts | 35 |
2 files changed, 0 insertions, 59 deletions
diff --git a/board/chromebook-x86/dts/alex.dts b/board/chromebook-x86/dts/alex.dts deleted file mode 100644 index 2f13544612..0000000000 --- a/board/chromebook-x86/dts/alex.dts +++ /dev/null @@ -1,24 +0,0 @@ -/dts-v1/; - -/include/ "coreboot.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Google Alex"; - compatible = "google,alex", "intel,atom-pineview"; - - config { - silent_console = <0>; - }; - - gpio: gpio {}; - - serial { - reg = <0x3f8 8>; - clock-frequency = <115200>; - }; - - chosen { }; - memory { device_type = "memory"; reg = <0 0>; }; -}; diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts deleted file mode 100644 index 4a37dac4ea..0000000000 --- a/board/chromebook-x86/dts/link.dts +++ /dev/null @@ -1,35 +0,0 @@ -/dts-v1/; - -/include/ "coreboot.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Google Link"; - compatible = "google,link", "intel,celeron-ivybridge"; - - config { - silent_console = <0>; - }; - - gpio: gpio {}; - - serial { - reg = <0x3f8 8>; - clock-frequency = <115200>; - }; - - chosen { }; - memory { device_type = "memory"; reg = <0 0>; }; - - spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - }; - }; -}; |