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authorPali Rohár <pali@kernel.org>2022-01-21 12:01:15 +0100
committerStefan Roese <sr@denx.de>2022-01-31 10:23:37 +0100
commit9ae831cedfa8f674731b794799703f672cfc9f24 (patch)
treeacd5545149983342ca70495f05010fbd9620286f /board/Marvell
parente267665a7420bddbfd5833573fdfc9d0930ff515 (diff)
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arm: mvebu: Espressobin: Fix URLs in comments
Use versioned URLs for line numbers as branches are moving in the time and use master branch for mv-ddr-marvell where is up-to-date code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/Marvell')
-rw-r--r--board/Marvell/mvebu_armada-37xx/board.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index d7b6ecafbf..6bfec0cc5b 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -59,11 +59,11 @@ DECLARE_GLOBAL_DATA_PTR;
* Memory Controller Registers
*
* Assembled based on public information:
- * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
+ * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/v2020.11.26/wtmi/main.c#L332-336
* https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
*
* And checked against the written register values for the various topologies:
- * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/master/a3700/mv_ddr_tim.h
*/
#define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
#define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf