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authorMadalin Bucur <madalin.bucur@oss.nxp.com>2020-04-30 16:00:13 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2020-06-04 18:53:20 +0530
commitffe706d9b8e9680e3a739400f233798e2012f5cd (patch)
treebe90c80e03a5cbd7273e5f65074fd72609d7ccdf /arch
parentcdc76f80ac4841ce9cc4584e0e603b3a993a3a8d (diff)
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powerpc: dts: add QorIQ DPAA 1 FMan v3 to T1024RDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the T1024RDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/dts/t1024rdb.dts54
1 files changed, 53 insertions, 1 deletions
diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
index 19a6652a23..32aaa4adaa 100644
--- a/arch/powerpc/dts/t1024rdb.dts
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -3,7 +3,7 @@
* T1024RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*/
/include/ "t102x.dtsi"
@@ -14,4 +14,56 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
+
+ aliases {
+ sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ fman@400000 {
+ fm1mac1: ethernet@e0000 {
+ phy-handle = <&xg_aqr105_phy3>;
+ phy-connection-type = "xgmii";
+ };
+
+ fm1mac2: ethernet@e2000 {
+ };
+
+ fm1mac3: ethernet@e4000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ fm1mac4: ethernet@e6000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio0: mdio@fc000 {
+ rgmii_phy1: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ rgmii_phy2: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+ };
+
+ xmdio0: mdio@fd000 {
+ xg_aqr105_phy3: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+ sg_2500_aqr105_phy4: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ };
+ };
+ };
+ };
+
};
+
+#include "t1024si-post.dtsi"