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authorJonas Karlman <jonas@kwiboo.se>2024-02-17 00:22:41 +0000
committerKever Yang <kever.yang@rock-chips.com>2024-03-14 11:40:48 +0800
commitaa321d49f7d5b9e6dd14cfdc7829d0bf5ea098cc (patch)
treedf4e891b3aaf93446b2c1c62fe4ca3694b6c66ae /arch
parenta37a3ddd515b751e495a488cbbdd4afaf32e7d30 (diff)
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rockchip: rk3328-orangepi-r1-plus: Enable boot from SPI NOR flash
Add Kconfig options to enable support for booting from SPI NOR flash on Orange Pi R1 Plus boards. The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx boards. => sf probe SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1376768 bytes read in 66 ms (19.9 MiB/s) => sf update ${fileaddr} 0 ${filesize} device 0 offset 0x0, size 0x150200 1126912 bytes written, 249856 bytes skipped in 14.22s, speed 100542 B/s Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi16
-rw-r--r--arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi16
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 7cdf691379..0dbe5a01f9 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -17,6 +17,22 @@
};
};
+&spi0m2_clk {
+ bootph-pre-ram;
+};
+
+&spi0m2_cs0 {
+ bootph-pre-ram;
+};
+
+&spi0m2_rx {
+ bootph-pre-ram;
+};
+
+&spi0m2_tx {
+ bootph-pre-ram;
+};
+
&vcc_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 35baeb2464..1af75ada1a 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -17,6 +17,22 @@
};
};
+&spi0m2_clk {
+ bootph-pre-ram;
+};
+
+&spi0m2_cs0 {
+ bootph-pre-ram;
+};
+
+&spi0m2_rx {
+ bootph-pre-ram;
+};
+
+&spi0m2_tx {
+ bootph-pre-ram;
+};
+
&vcc_sd {
bootph-pre-ram;
};