ARM: uniphier: add PH1-LD20 SoC support

This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

35 files changed, 888 insertions, 3 deletions

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 4724af58a1..87d1675ffc 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
 	select CPU_V7
 
+config ARCH_UNIPHIER_LD20
+	bool "UniPhier PH1-LD20 SoC"
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 endchoice
 
 config ARCH_UNIPHIER_LD4
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 35edca1015..774ea9985a 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
 
 obj-$(CONFIG_CPU_V7) += arm32/
+obj-$(CONFIG_ARM64) += arm64/
diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile
new file mode 100644
index 0000000000..5ed030ae40
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += timer.o
+else
+obj-y += mem_map.o smp.o smp_kick_cpus.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
+endif
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
new file mode 100644
index 0000000000..607f96a58d
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -0,0 +1,41 @@
+/*
+ * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CCI500_BASE			0x5FD00000
+#define CCI500_SLAVE_OFFSET		0x1000
+
+#define CCI500_SNOOP_CTRL
+#define   CCI500_SNOOP_CTRL_EN_DVM	BIT(1)
+#define   CCI500_SNOOP_CTRL_EN_SNOOP	BIT(0)
+
+void cci500_init(unsigned int nr_slaves)
+{
+	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
+	int i;
+
+	for (i = 0; i < nr_slaves; i++) {
+		void __iomem *base;
+		u32 tmp;
+
+		base = map_sysmem(slave_base, SZ_4K);
+
+		tmp = readl(base);
+		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
+		writel(tmp, base);
+
+		unmap_sysmem(base);
+
+		slave_base += CCI500_SLAVE_OFFSET;
+	}
+}
diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c
new file mode 100644
index 0000000000..74ef91984c
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/mem_map.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region uniphier_mem_map[] = {
+	{
+		.base = 0x00000000,
+		.size = 0x80000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.base = 0x80000000,
+		.size = 0xc0000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+	{ /* sentinel */ }
+};
+
+struct mm_region *mem_map = uniphier_mem_map;
diff --git a/arch/arm/mach-uniphier/arm64/smp.S b/arch/arm/mach-uniphier/arm64/smp.S
new file mode 100644
index 0000000000..9348ec97c4
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/smp.S
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(uniphier_smp_setup)
+	mrs	x0, s3_1_c15_c2_1	/* CPUECTLR_EL1 */
+	orr	x0, x0, #(1 << 6)	/* SMPEN */
+	msr	s3_1_c15_c2_1, x0
+	ret
+ENDPROC(uniphier_smp_setup)
+
+ENTRY(uniphier_secondary_startup)
+	bl	uniphier_smp_setup
+	b	_start
+ENDPROC(uniphier_secondary_startup)
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
new file mode 100644
index 0000000000..64412e0ecc
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define UNIPHIER_SMPCTRL_ROM_RSV0	0x59801200
+
+void uniphier_smp_setup(void);
+void uniphier_secondary_startup(void);
+
+void uniphier_smp_kick_all_cpus(void)
+{
+	void __iomem *rom_boot_rsv0;
+
+	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
+
+	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
+	readq(rom_boot_rsv0);	/* relax */
+
+	unmap_sysmem(rom_boot_rsv0);
+
+	uniphier_smp_setup();
+
+	asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+}
diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c
new file mode 100644
index 0000000000..4beab9dca8
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/timer.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CNT_CONTROL_BASE	0x60E00000
+
+#define CNTCR			0x000
+#define   CNTCR_EN			BIT(0)
+
+/* setup ARMv8 Generic Timer */
+int timer_init(void)
+{
+	void __iomem *base;
+	u32 tmp;
+
+	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
+
+	/*
+	 * Note:
+	 * In a system that implements both Secure and Non-secure states,
+	 * this register is only writable in Secure state.
+	 */
+	tmp = readl(base + CNTCR);
+	tmp |= CNTCR_EN;
+	writel(tmp, base + CNTCR);
+
+	unmap_sysmem(base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
index 020ffcae1d..330d690bab 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -8,9 +8,13 @@
 
 #include "micro-support-card.h"
 
+void uniphier_smp_kick_all_cpus(void);
+
 int board_init(void)
 {
 	led_puts("Uboo");
-
+#ifdef CONFIG_ARM64
+	uniphier_smp_kick_all_cpus();
+#endif
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 6f2adf1b13..2a7ae1b529 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -62,6 +62,14 @@ int board_early_init_f(void)
 		uniphier_pxs2_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_pin_init();
+		led_puts("U1");
+		uniphier_ld20_clk_init();
+		cci500_init(2);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 0d2b94de11..f0547c336e 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_data = {
+	.dram_freq = 1866,
+	.dram_nr_ch = 3,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[1] = {
+		.base = 0xc0000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[2] = {
+		.base = 0x100000000UL,
+		.size = 0x40000000,
+		.width = 32,
+	},
+};
+#endif
+
 struct uniphier_board_id {
 	const char *compatible;
 	const struct uniphier_board_data *param;
@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
+#endif
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 278df64ad5..6cd096ec5f 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h
index 2e05a47f70..bd44d73416 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h
@@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void);
 u32 uniphier_ld4_boot_device(void);
 u32 uniphier_pro5_boot_device(void);
 u32 uniphier_pxs2_boot_device(void);
+u32 uniphier_ld20_boot_device(void);
 
 void uniphier_sld3_boot_mode_show(void);
 void uniphier_ld4_boot_mode_show(void);
 void uniphier_pro5_boot_mode_show(void);
 void uniphier_pxs2_boot_mode_show(void);
+void uniphier_ld20_boot_mode_show(void);
 
 u32 spl_boot_device_raw(void);
 
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
new file mode 100644
index 0000000000..100275e6cb
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 5)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_ld20_boot_device(void)
+{
+	int boot_mode;
+
+	if (~readl(SG_PINMON0) & 0x00000780)
+		return BOOT_DEVICE_USB;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
+
+void uniphier_ld20_boot_mode_show(void)
+{
+	int mode_sel, i;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+		       boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index b08cd6c404..48e478c5d1 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -39,6 +39,10 @@ u32 spl_boot_device_raw(void)
 	case SOC_UNIPHIER_LD6B:
 		return uniphier_pxs2_boot_device();
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		return uniphier_ld20_boot_device();
+#endif
 	default:
 		return BOOT_DEVICE_NONE;
 	}
diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index bccab62442..fa97dc5856 100644
--- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -39,6 +39,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		uniphier_pxs2_boot_mode_show();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_boot_mode_show();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 1d736a5c0f..93e9d91e47 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
new file mode 100644
index 0000000000..556a30ae01
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+void uniphier_ld20_clk_init(void)
+{
+}
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index aae8d1fabd..f9646c0205 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -48,7 +48,7 @@ int print_cpuinfo(void)
 		puts("PH1-LD11 ()");
 		break;
 	case 0x32:
-		puts("PH1-LD20 ()");
+		puts("PH1-LD20 (SC1401AJ1)");
 		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 615ba2cce9..41aa53b6b5 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= umc-sld8.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= umc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= umc-ld20.o
 
 else
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
new file mode 100644
index 0000000000..b1b4cb0d94
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef _DDRPHY_LD20_REGS_H
+#define _DDRPHY_LD20_REGS_H
+
+#define PHY_SCL_DATA_0			0x00000104
+#define PHY_SCL_DATA_1			0x00000108
+#define PHY_SCL_LATENCY			0x0000010C
+#define PHY_SCL_START			0x00000100
+#define PHY_SCL_CONFIG_1		0x00000118
+#define PHY_SCL_CONFIG_2		0x0000011C
+#define PHY_PAD_CTRL			0x00000120
+#define PHY_DLL_RECALIB			0x00000124
+#define PHY_DLL_ADRCTRL			0x00000128
+#define PHY_LANE_SEL			0x0000012C
+#define PHY_DLL_TRIM_1			0x00000130
+#define PHY_DLL_TRIM_2			0x00000134
+#define PHY_DLL_TRIM_3			0x00000138
+#define PHY_SCL_MAIN_CLK_DELTA		0x00000140
+#define PHY_WRLVL_AUTOINC_TRIM		0x0000014C
+#define PHY_WRLVL_DYN_ODT		0x00000150
+#define PHY_WRLVL_ON_OFF		0x00000154
+#define PHY_UNQ_ANALOG_DLL_1		0x0000015C
+#define PHY_DLL_INCR_TRIM_1		0x00000164
+#define PHY_DLL_INCR_TRIM_3		0x00000168
+#define PHY_SCL_CONFIG_3		0x0000016C
+#define PHY_UNIQUIFY_TSMC_IO_1		0x00000170
+#define PHY_SCL_START_ADDR		0x00000188
+#define PHY_DSCL_CNT		        0x0000019C
+#define PHY_DLL_TRIM_CLK		0x000001A4
+#define PHY_DYNAMIC_BIT_LVL		0x000001AC
+#define PHY_SCL_WINDOW_TRIM		0x000001B4
+#define PHY_DISABLE_GATING_FOR_SCL	0x000001B8
+#define PHY_SCL_CONFIG_4		0x000001BC
+#define PHY_DYNAMIC_WRITE_BIT_LVL	0x000001C0
+#define PHY_VREF_TRAINING		0x000001C8
+#define PHY_SCL_GATE_TIMING		0x000001E0
+
+#endif /* _DDRPHY_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
new file mode 100644
index 0000000000..46e513cd09
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef UMC_LD20_REGS_H
+#define UMC_LD20_REGS_H
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_CMDCTLC		0x00000008
+#define UMC_INITCTLA		0x00000020
+#define UMC_INITCTLB		0x00000024
+#define UMC_INITCTLC		0x00000028
+#define UMC_DRMMR0		0x00000030
+#define UMC_DRMMR1		0x00000034
+#define UMC_DRMMR2		0x00000038
+#define UMC_DRMMR3		0x0000003C
+#define UMC_INITSET		0x00000040
+#define UMC_INITSTAT		0x00000044
+#define UMC_CMDCTLE		0x00000050
+#define UMC_SPCSETB		0x00000084
+#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
+#define UMC_ACSCTLA		0x000000C0
+#define UMC_ACSSETA		0x000000C4
+#define UMC_MEMCONF0A		0x00000200
+#define UMC_MEMCONF0B		0x00000204
+#define UMC_MEMCONFCH		0x00000240
+#define UMC_MEMMAPSET		0x00000250
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_ODTCTL_D0		0x00000618
+#define UMC_ODTCTL_D1		0x0000061C
+#define UMC_RESPCTL		0x00000624
+#define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_ERRMASKA		0x00000958
+#define UMC_ERRMASKB		0x0000095C
+#define UMC_BSICMAPSET		0x00000988
+#define UMC_DIOCTLA		0x00000C00
+#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
+#define UMC_DFISTCTLC		0x00000C18
+#define UMC_DFICUPDCTLA		0x00000C20
+#define UMC_DFIPUPDCTLA		0x00000C30
+#define UMC_DFICSOVRRD		0x00000C84
+#define UMC_DFITURNOFF          0x00000C88
+
+/* UM registers */
+#define UMC_MBUS0		0x00080004
+#define UMC_MBUS1		0x00081004
+#define UMC_MBUS2		0x00082004
+#define UMC_MBUS3		0x00000C78
+#define UMC_MBUS4		0x00000CF8
+#define UMC_MBUS5		0x00000E78
+#define UMC_MBUS6		0x00000EF8
+#define UMC_MBUS7		0x00001278
+#define UMC_MBUS8		0x000012F8
+#define UMC_MBUS9		0x00002478
+#define UMC_MBUS10		0x000024F8
+
+#endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
new file mode 100644
index 0000000000..4614dac5d2
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-ld20-regs.h"
+#include "umc-ld20-regs.h"
+
+#define DRAM_CH_NR	3
+
+enum dram_freq {
+	DRAM_FREQ_1866M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+
+static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
+static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+	{0x0049071D, 0x0078071D},
+};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+
+static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static u32 umc_directbusctrla[DRAM_CH_NR] = {
+	0x00000000, 0x00000001, 0x00000001
+};
+
+/* DDR PHY */
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+{
+	writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+	while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000006, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x0000000c, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000012, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
+	writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
+	writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
+	writel(0x00000070, phy_base + PHY_VREF_TRAINING);
+	writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
+	writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
+	writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
+	writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
+	writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
+	writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
+	writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
+	writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
+	writel(0x00005076, phy_base + PHY_SCL_LATENCY);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+	writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
+	writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
+	writel(0x50000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
+	writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x30500000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
+	writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
+	writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x34000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+
+	return 0;
+}
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+		       unsigned long size, int ch)
+{
+	enum dram_size size_e;
+
+	switch (size) {
+	case 0:
+		return 0;
+	case SZ_256M:
+		size_e = DRAM_SZ_256M;
+		break;
+	case SZ_512M:
+		size_e = DRAM_SZ_512M;
+		break;
+	default:
+		pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
+		       size, ch);
+		return -EINVAL;
+	}
+
+	/* Wait for PHY Init Complete */
+	while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
+		cpu_relax();
+
+	writel(0x00000001, dc_base + UMC_DFICSOVRRD);
+	writel(0x00000000, dc_base + UMC_DFITURNOFF);
+
+	writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
+	writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
+	writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
+
+	writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
+	writel(0x00000004, dc_base + UMC_DRMMR1);
+	writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
+	writel(0x00000000, dc_base + UMC_DRMMR3);
+
+	writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
+	writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
+	writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+	writel(0x00000008, dc_base + UMC_MEMMAPSET);
+
+	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+	writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+	writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+	writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
+
+	writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+	writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+	writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+	writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+	writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+	writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+	writel(umc_dataset[freq], dc_base + UMC_DATASET);
+
+	writel(0x00400020, dc_base + UMC_DCCGCTL);
+	writel(0x00000003, dc_base + UMC_ACSCTLA);
+	writel(0x00000103, dc_base + UMC_FLOWCTLG);
+	writel(0x00010200, dc_base + UMC_ACSSETA);
+
+	writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
+	writel(0x00004444, dc_base + UMC_FLOWCTLC);
+	writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
+
+	writel(0x00202000, dc_base + UMC_FLOWCTLB);
+	writel(0x00000000, dc_base + UMC_BSICMAPSET);
+	writel(0x00000000, dc_base + UMC_ERRMASKA);
+	writel(0x00000000, dc_base + UMC_ERRMASKB);
+
+	writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
+
+	writel(0x00000001, dc_base + UMC_INITSET);
+	/* Wait for PHY Init Complete */
+	while (readl(dc_base + UMC_INITSTAT) & BIT(0))
+		cpu_relax();
+
+	writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
+	writel(0x00000000, dc_base + UMC_DFICSOVRRD);
+
+	return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
+		       enum dram_freq freq, unsigned long size, int ch)
+{
+	void __iomem *dc_base = umc_ch_base + 0x00011000;
+	void __iomem *phy_base = phy_ch_base;
+	int ret;
+
+	/* PHY Update Mode (ON) */
+	writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
+
+	/* deassert PHY reset signals */
+	writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+	       dc_base + UMC_DIOCTLA);
+
+	ddrphy_init(phy_base, freq);
+
+	ret = umc_dc_init(dc_base, freq, size, ch);
+	if (ret)
+		return ret;
+
+	ret = ddrphy_training(phy_base);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+	writel(0x000000ff, um_base + UMC_MBUS0);
+	writel(0x000000ff, um_base + UMC_MBUS1);
+	writel(0x000000ff, um_base + UMC_MBUS2);
+	writel(0x00000001, um_base + UMC_MBUS3);
+	writel(0x00000001, um_base + UMC_MBUS4);
+	writel(0x00000001, um_base + UMC_MBUS5);
+	writel(0x00000001, um_base + UMC_MBUS6);
+	writel(0x00000001, um_base + UMC_MBUS7);
+	writel(0x00000001, um_base + UMC_MBUS8);
+	writel(0x00000001, um_base + UMC_MBUS9);
+	writel(0x00000001, um_base + UMC_MBUS10);
+}
+
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
+{
+	void __iomem *um_base = (void __iomem *)0x5b600000;
+	void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
+	void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
+	enum dram_freq freq;
+	int ch, ret;
+
+	switch (bd->dram_freq) {
+	case 1866:
+		freq = DRAM_FREQ_1866M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+		return -EINVAL;
+	}
+
+	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+		unsigned long size = bd->dram_ch[ch].size;
+		unsigned int width = bd->dram_ch[ch].width;
+
+		ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
+				  size / (width / 16), ch);
+		if (ret) {
+			pr_err("failed to initialize UMC ch%d\n", ch);
+			return ret;
+		}
+
+		umc_ch_base += 0x00200000;
+		phy_ch_base += 0x00004000;
+	}
+
+	um_init(um_base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 59058cdb1f..9242b416c5 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
new file mode 100644
index 0000000000..37adb37a1f
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL7);
+	tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
+		SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
+		SC_RSTCTRL7_UMC30;
+	writel(tmp, SC_RSTCTRL7);
+
+	/* provide clocks */
+	tmp = readl(SC_CLKCTRL7);
+	tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
+							SC_CLKCTRL7_UMC30;
+	writel(tmp, SC_CLKCTRL7);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 3abf4aadc4..f5b3fa836c 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
@@ -86,6 +87,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
 
@@ -93,6 +95,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
 
 void uniphier_sld3_pin_init(void);
 void uniphier_ld4_pin_init(void);
@@ -101,11 +104,15 @@ void uniphier_sld8_pin_init(void);
 void uniphier_pro5_pin_init(void);
 void uniphier_pxs2_pin_init(void);
 void uniphier_ld6b_pin_init(void);
+void uniphier_ld20_pin_init(void);
 
 void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
+void uniphier_ld20_clk_init(void);
+
+void cci500_init(int nr_slaves);
 
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index 34b15e3427..b58e6c885a 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= init-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= init-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= init-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= init-ld20.o
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
new file mode 100644
index 0000000000..0ad264c9f1
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld20_init(const struct uniphier_board_data *bd)
+{
+	uniphier_sbc_init_savepin(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+	uniphier_pxs2_memconf_init(bd);
+
+	led_puts("L1");
+
+	uniphier_ld20_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	{
+		int res;
+
+		res = uniphier_ld20_umc_init(bd);
+		if (res < 0) {
+			while (1)
+				;
+		}
+	}
+
+	led_puts("L5");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index c56c44c070..15a53ce068 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -55,6 +55,11 @@ void spl_board_init(void)
 		uniphier_pxs2_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_init(param);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
index 78bb677dd4..6ed14199de 100644
--- a/arch/arm/mach-uniphier/memconf/Makefile
+++ b/arch/arm/mach-uniphier/memconf/Makefile
@@ -6,3 +6,4 @@ obj-y					+= memconf.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= memconf-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= memconf-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= memconf-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= memconf-pxs2.o
diff --git a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
index bf14d0d283..e98eb48e04 100644
--- a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
@@ -49,6 +49,9 @@ int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
 	case SZ_512M:
 		tmp |= SG_MEMCONF_CH2_SZ_512M;
 		break;
+	case SZ_1G:
+		tmp |= SG_MEMCONF_CH2_SZ_1G;
+		break;
 	default:
 		pr_err("error: unsupported DRAM Ch2 size\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index 5504c24c3d..b579cb06e7 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pinctrl-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= pinctrl-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= pinctrl-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
new file mode 100644
index 0000000000..6066b169cf
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld20_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(3, 0, 8, 4);	/* XNFWP   -> XNFWP */
+	sg_set_pinsel(4, 0, 8, 4);	/* XNFCE0  -> XNFCE0 */
+	sg_set_pinsel(5, 0, 8, 4);	/* NFRYBY0 -> NFRYBY0 */
+	sg_set_pinsel(6, 0, 8, 4);	/* XNFRE   -> XNFRE */
+	sg_set_pinsel(7, 0, 8, 4);	/* XNFWE   -> XNFWE */
+	sg_set_pinsel(8, 0, 8, 4);	/* NFALE   -> NFALE */
+	sg_set_pinsel(9, 0, 8, 4);	/* NFCLE   -> NFCLE */
+	sg_set_pinsel(10, 0, 8, 4);	/* NFD0    -> NFD0 */
+	sg_set_pinsel(11, 0, 8, 4);	/* NFD1    -> NFD1 */
+	sg_set_pinsel(12, 0, 8, 4);	/* NFD2    -> NFD2 */
+	sg_set_pinsel(13, 0, 8, 4);	/* NFD3    -> NFD3 */
+	sg_set_pinsel(14, 0, 8, 4);	/* NFD4    -> NFD4 */
+	sg_set_pinsel(15, 0, 8, 4);	/* NFD5    -> NFD5 */
+	sg_set_pinsel(16, 0, 8, 4);	/* NFD6    -> NFD6 */
+	sg_set_pinsel(17, 0, 8, 4);	/* NFD7    -> NFD7 */
+	sg_set_iectrl_range(3, 17);
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(46, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(47, 0, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(48, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(49, 0, 8, 4);	/* USB1OD   -> USB1OD */
+	sg_set_pinsel(50, 0, 8, 4);	/* USB2VBUS -> USB2VBUS */
+	sg_set_pinsel(51, 0, 8, 4);	/* USB2OD   -> USB2OD */
+	sg_set_pinsel(52, 0, 8, 4);	/* USB3VBUS -> USB3VBUS */
+	sg_set_pinsel(53, 0, 8, 4);	/* USB3OD   -> USB3OD */
+	sg_set_iectrl_range(46, 53);
+#endif
+}
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index e515af9439..3c1e92a54d 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 4044245ee1..1d71ce87ae 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -50,10 +50,11 @@
 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
+/* PH1-LD6b, ProXstream2, PH1-LD20 only */
 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)