Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1021aqds.h
	include/configs/ls1021atwr.h

16 files changed, 338 insertions, 58 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d3303bdae..ada221778c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -656,6 +656,7 @@ config TARGET_VEXPRESS64_JUNO
 
 config TARGET_LS2080A_EMU
 	bool "Support ls2080a_emu"
+	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -666,6 +667,7 @@ config TARGET_LS2080A_EMU
 
 config TARGET_LS2080A_SIMU
 	bool "Support ls2080a_simu"
+	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -676,6 +678,7 @@ config TARGET_LS2080A_SIMU
 
 config TARGET_LS2080AQDS
 	bool "Support ls2080aqds"
+	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -687,6 +690,7 @@ config TARGET_LS2080AQDS
 
 config TARGET_LS2080ARDB
 	bool "Support ls2080ardb"
+	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -740,6 +744,8 @@ config TARGET_LS1012AFRDM
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
@@ -748,6 +754,8 @@ config TARGET_LS1021AQDS
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0d4bfbc55b..c1eeefd5dd 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 920eb4ad98..28bf778d9c 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,6 +1,89 @@
 config ARCH_LS1021A
-	bool "Freescale Layerscape LS1021A SoC"
+	bool
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_DDR_VER_50
+
+menu "LS102xA architecture"
+	depends on ARCH_LS1021A
 
 config LS1_DEEP_SLEEP
-	bool "Freescale Layerscape 1 deep sleep"
+	bool "Deep sleep"
+	depends on ARCH_LS1021A
+
+config MAX_CPUS
+	int "Maximum number of CPUs permitted for LS102xA"
+	depends on ARCH_LS1021A
+	default 2
+	help
+	  Set this number to the maximum number of possible CPUs in the SoC.
+	  SoCs may have multiple clusters with each cluster may have multiple
+	  ports. If some ports are reserved but higher ports are used for
+	  cores, count the reserved ports. This will allocate enough memory
+	  in spin table to properly handle all cores.
+
+config NUM_DDR_CONTROLLERS
+	int "Maximum DDR controllers"
+	default 1
+
+config SYS_FSL_ERRATUM_A010315
+	bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_SRDS_1
+	bool
+
+config SYS_FSL_SRDS_2
+	bool
+
+config SYS_HAS_SERDES
+	bool
+
+config SYS_FSL_DDR
+	bool "Freescale DDR driver"
+	help
+	  Select Freescale General DDR driver, shared between most Freescale
+	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+	  based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+	bool
+	default y
+	help
+	  Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_VER
+	int
+	default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+	bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+	bool
+
+config SYS_FSL_DDRC_GEN4
+	bool
+
+config SYS_FSL_DDR3
+	bool "Freescale DDR3 controller"
+	depends on !SYS_FSL_DDR4
+	select SYS_FSL_DDR
+	select SYS_FSL_DDRC_ARM_GEN3
+	help
+	  Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+	bool "Freescale DDR4 controller"
+	select SYS_FSL_DDR
+	select SYS_FSL_DDRC_GEN4
+	help
+	  Enable Freescale DDR4 controller.
+
+config SYS_FSL_IFC_BANK_COUNT
+	int "Maximum banks of Integrated flash controller"
+	depends on ARCH_LS1021A
+	default 8
+
+endmenu
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 31f00cbd69..52fb6f8d51 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,10 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
+void s_init(void)
+{
+}
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 void erratum_a010315(void)
 {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f8057baa03..94ec8d502b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,17 +1,138 @@
 config ARCH_LS1012A
-	bool "Freescale Layerscape LS1012A SoC"
+	bool
+	select FSL_LSCH2
+	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
 
 config ARCH_LS1043A
-	bool "Freescale Layerscape LS1043A SoC"
+	bool
+	select FSL_LSCH2
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_ERRATUM_A010539
 
 config ARCH_LS1046A
-	bool "Freescale Layerscape LS1046A SoC"
+	bool
+	select FSL_LSCH2
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_DDR4
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_ERRATUM_A010539
+	select SYS_FSL_SRDS_2
+
+config ARCH_LS2080A
+	bool
+	select FSL_LSCH3
+	select SYS_FSL_DDR4
+	select SYS_FSL_DDR_LE
+	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_HAS_DP_DDR
+	select SYS_FSL_SRDS_2
+
+config FSL_LSCH2
+	bool
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
+
+config FSL_LSCH3
+	bool
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
+
+menu "Layerscape architecture"
+	depends on FSL_LSCH2 || FSL_LSCH3
 
 config SYS_FSL_MMDC
-	bool "Freescale Multi Mode DDR Controller"
+	bool
 
 config SYS_FSL_ERRATUM_A010315
 	bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_ERRATUM_A010539
+	bool "Workaround for PIN MUX erratum A010539"
+
+config MAX_CPUS
+	int "Maximum number of CPUs permitted for Layerscape"
+	default 4 if ARCH_LS1043A
+	default 4 if ARCH_LS1046A
+	default 16 if ARCH_LS2080A
+	default 1
+	help
+	  Set this number to the maximum number of possible CPUs in the SoC.
+	  SoCs may have multiple clusters with each cluster may have multiple
+	  ports. If some ports are reserved but higher ports are used for
+	  cores, count the reserved ports. This will allocate enough memory
+	  in spin table to properly handle all cores.
+
+config NUM_DDR_CONTROLLERS
+	int "Maximum DDR controllers"
+	default 3 if ARCH_LS2080A
+	default 1
+
+config SYS_FSL_IFC_BANK_COUNT
+	int "Maximum banks of Integrated flash controller"
+	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+	default 4 if ARCH_LS1043A
+	default 4 if ARCH_LS1046A
+	default 8 if ARCH_LS2080A
+
+config SYS_FSL_HAS_DP_DDR
+	bool
+
+config SYS_FSL_SRDS_1
+	bool
+
+config SYS_FSL_SRDS_2
+	bool
+
+config SYS_HAS_SERDES
+	bool
+
+config SYS_FSL_DDR
+	bool "Freescale DDR driver"
+	help
+	  Select Freescale General DDR driver, shared between most Freescale
+	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+	  based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+	bool
+	help
+	  Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_LE
+	bool
+	help
+	  Access DDR registers in little-endian.
+
+config SYS_FSL_DDR_VER
+	int
+	default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+	bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+	bool
+
+config SYS_FSL_DDRC_GEN4
+	bool
+
+config SYS_FSL_DDR3
+	bool "Freescale DDR3 controller"
+	depends on !SYS_FSL_DDR4
+	select SYS_FSL_DDR
+	select SYS_FSL_DDRC_ARM_GEN3
+	help
+	  Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+	bool "Freescale DDR4 controller"
+	select SYS_FSL_DDR
+	select SYS_FSL_DDRC_GEN4
+	help
+	  Enable Freescale DDR4 controller.
+
+endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index f865373df3..b7a2e0c946 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -44,6 +44,9 @@ void cpu_name(char *name)
 
 			if (IS_E_PROCESSOR(svr))
 				strcat(name, "E");
+
+			sprintf(name + strlen(name), " Rev%d.%d",
+				SVR_MAJ(svr), SVR_MIN(svr));
 			break;
 		}
 
@@ -200,6 +203,27 @@ static inline u32 initiator_type(u32 cluster, int init_id)
 	return 0;
 }
 
+u32 cpu_pos_mask(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0;
+	u32 cluster, type, mask = 0;
+
+	do {
+		int j;
+
+		cluster = gur_in32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
+				mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
+
+	return mask;
+}
+
 u32 cpu_mask(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 40d6a761e8..1a8321b0e4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -108,6 +108,24 @@ remove_psci_node:
 }
 #endif
 
+void fsl_fdt_disable_usb(void *blob)
+{
+	int off;
+	/*
+	 * SYSCLK is used as a reference clock for USB. When the USB
+	 * controller is used, SYSCLK must meet the additional requirement
+	 * of 100 MHz.
+	 */
+	if (CONFIG_SYS_CLK_FREQ != 100000000) {
+		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+		while (off != -FDT_ERR_NOTFOUND) {
+			fdt_status_disabled(blob, off);
+			off = fdt_node_offset_by_compatible(blob, off,
+							    "snps,dwc3");
+		}
+	}
+}
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -150,4 +168,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
+	fsl_fdt_disable_usb(blob);
+
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index df7ffb88f6..f607c3900a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -104,6 +104,11 @@ int is_core_valid(unsigned int core)
 	return !!((1 << core) & cpu_mask());
 }
 
+static int is_pos_valid(unsigned int pos)
+{
+	return !!((1 << pos) & cpu_pos_mask());
+}
+
 int is_core_online(u64 cpu_id)
 {
 	u64 *table;
@@ -126,9 +131,9 @@ int cpu_disable(int nr)
 	return 0;
 }
 
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
 {
-	u32 cores = cpu_mask();
+	u32 cores = cpu_pos_mask();
 	int i, count = 0;
 
 	if (nr == 0) {
@@ -139,14 +144,17 @@ int core_to_pos(int nr)
 	}
 
 	for (i = 1; i < 32; i++) {
-		if (is_core_valid(i)) {
+		if (is_pos_valid(i)) {
 			count++;
 			if (count == nr)
 				break;
 		}
 	}
 
-	return count;
+	if (count != nr)
+		return -1;
+
+	return i;
 }
 
 int cpu_status(int nr)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 463d1e30d2..d68eeba349 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -233,9 +233,8 @@ int sata_init(void)
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 #endif
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
-	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA);
 	scsi_scan(0);
@@ -321,6 +320,19 @@ void erratum_a010315(void)
 }
 #endif
 
+static void erratum_a010539(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 porsr1;
+
+	porsr1 = in_be32(&gur->porsr1);
+	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
+	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+		 porsr1);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -339,7 +351,9 @@ void fsl_lsch2_early_init_f(void)
 #endif
 	/* Make SEC reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-		     SCFG_SNPCNFGCR_SECWRSNP);
+		     SCFG_SNPCNFGCR_SECWRSNP |
+		     SCFG_SNPCNFGCR_SATARDSNP |
+		     SCFG_SNPCNFGCR_SATAWRSNP);
 
 	/*
 	 * Enable snoop requests and DVM message requests for
@@ -352,6 +366,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a008850_early(); /* part 1 of 2 */
 	erratum_a009929();
 	erratum_a009660();
+	erratum_a010539();
 }
 #endif
 
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index a8bffbafa7..f038f96171 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -215,5 +215,26 @@
 			big-endian;
 			status = "disabled";
 		};
+
+		usb0: usb3@2f00000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x2f00000 0x0 0x10000>;
+			interrupts = <0 60 0x4>;
+			dr_mode = "host";
+		};
+
+		usb1: usb3@3000000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3000000 0x0 0x10000>;
+			interrupts = <0 61 0x4>;
+			dr_mode = "host";
+		};
+
+		usb2: usb3@3100000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 63 0x4>;
+			dr_mode = "host";
+		};
 	};
 };
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index b308c8b982..f76e981c54 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -75,4 +75,18 @@
 		reg-names = "QuadSPI", "QuadSPI-memory";
 		num-cs = <4>;
 	};
+
+	usb0: usb3@3100000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3100000 0x0 0x10000>;
+		interrupts = <0 80 0x4>; /* Level high type */
+		dr_mode = "host";
+	};
+
+	usb1: usb3@3110000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3110000 0x0 0x10000>;
+		interrupts = <0 81 0x4>; /* Level high type */
+		dr_mode = "host";
+	};
 };
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index a5c6c4cd26..4201e0fbec 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -12,17 +12,6 @@
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80300000
 
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
-#endif
-
-#ifndef CONFIG_ARCH_LS1012A
-#define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
-#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
-#endif
-
 /*
  * Reserve secure memory
  * To be aligned with MMU block size
@@ -30,14 +19,8 @@
 #define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
 
 #ifdef CONFIG_LS2080A
-#define CONFIG_MAX_CPUS				16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		3
-#define CONFIG_SYS_FSL_HAS_DP_DDR		/* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE		0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
@@ -48,7 +31,6 @@
 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 
@@ -152,7 +134,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */
@@ -167,17 +148,12 @@
 #define CONFIG_SYS_FSL_PEX_LUT_BE
 #define CONFIG_SYS_FSL_SEC_BE
 
-#define CONFIG_SYS_FSL_SRDS_1
-
 /* SoC related */
 #ifdef CONFIG_LS1043A
-#define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1
 #define CONFIG_SYS_NUM_FM1_DTSEC		7
 #define CONFIG_SYS_NUM_FM1_10GEC		1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
 
@@ -206,23 +182,18 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_MAX_CPUS                         1
 #undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 #elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1
 #define CONFIG_SYS_NUM_FM1_DTSEC		8
 #define CONFIG_SYS_NUM_FM1_10GEC		2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SNVS_LE
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index df5187195d..d88543d063 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -168,6 +168,8 @@ struct sys_info {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1		0x0
+
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
@@ -335,6 +337,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index e46e076f16..f7306ff266 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
 int is_core_online(u64 cpu_id);
+u32 cpu_pos_mask(void);
 #endif
 #endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 4512732f79..58e90d8d88 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -60,9 +60,8 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
-#define AHCI_PORT_PHY_2_CFG    0x28184d1f
-#define AHCI_PORT_PHY_3_CFG    0x0e081509
 #define AHCI_PORT_TRANS_CFG    0x08000029
+#define AHCI_PORT_AXICC_CFG	0x3fffffff
 
 /* AHCI (sata) register map */
 struct ccsr_ahci {
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index fab8774028..ec65cc0bb2 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -94,14 +94,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008407
 
 #ifdef CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
-#endif
-#define CONFIG_SYS_FSL_DDR
 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
 #endif
@@ -120,13 +113,7 @@
 
 #define DCU_LAYER_MAX_NUM			16
 
-#define CONFIG_SYS_FSL_SRDS_1
-
 #ifdef CONFIG_LS102XA
-#define CONFIG_MAX_CPUS				2
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#define CONFIG_NUM_DDR_CONTROLLERS		1
-#define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_FSL_ERRATUM_A008378