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| author | Marek Vasut <marex@denx.de> | 2021-08-09 14:06:04 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2021-08-16 10:49:35 +0200 |
| commit | 59f6eb477e053355718fa25b3bce956991f016b8 (patch) | |
| tree | f5c8547bdbf8607349017d3be46f9b7230f83619 /arch | |
| parent | df686207437f73ca732983dfaf0bb43983e78c3f (diff) | |
| download | u-boot-59f6eb477e053355718fa25b3bce956991f016b8.tar.gz u-boot-59f6eb477e053355718fa25b3bce956991f016b8.tar.bz2 u-boot-59f6eb477e053355718fa25b3bce956991f016b8.zip | |
ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.
There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex for SPL, so opt for the second option. This incurs 20ms delay
during boot, when SPL loads U-Boot to DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi index 64299df816..94cf80dbed 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi @@ -198,7 +198,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; }; |