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| author | Harald Seiler <hws@denx.de> | 2020-12-15 16:47:51 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-03-02 14:03:02 -0500 |
| commit | 3394f398b5f37d930b9ae1b6638fe26b0cc735d8 (patch) | |
| tree | b9365954b8f41e456abd8082b377a1781a2190df /arch | |
| parent | 10b86ef9b347c72ad8e73e739a9a00efd0f259f6 (diff) | |
| download | u-boot-3394f398b5f37d930b9ae1b6638fe26b0cc735d8.tar.gz u-boot-3394f398b5f37d930b9ae1b6638fe26b0cc735d8.tar.bz2 u-boot-3394f398b5f37d930b9ae1b6638fe26b0cc735d8.zip | |
Revert "lpc32xx: cpu: add support for soft reset"
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The parameter passed to reset_cpu() no longer holds a meaning as all
call-sites now pass the value 0. Thus, branching on it is essentially
dead code and will just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now.
This is a preparation for removal of the reset_cpu() parameter across
the entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset")
Cc: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Harald Seiler <hws@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-lpc32xx/cpu.c | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 32af620605..7378192a33 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -22,23 +22,12 @@ void reset_cpu(ulong addr) /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - /* To be compatible with the original U-Boot code: - * addr: - 0: perform hard reset. - * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ - if (addr == 0) { - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse); - /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 - | WDTIM_MCTRL_M_RES2, &wdt->mctrl); - } else { - /* Force match output active */ - writel(0x01, &wdt->emr); - - /* Internal reset on match output (no pulse on "RESOUT_N") */ - writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); - } + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, + &wdt->mctrl); while (1) /* NOP */; |