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| author | Zhao Qiang <B45475@freescale.com> | 2013-10-12 13:46:33 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
| commit | 287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a (patch) | |
| tree | 638da6ca13c77d494a81603d18ea9c1f7feddc25 /arch | |
| parent | 787964b8118b47a50bda796a315068639977c884 (diff) | |
| download | u-boot-287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a.tar.gz u-boot-287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a.tar.bz2 u-boot-287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a.zip | |
PCIe:change the method to get the address of a requested capability in configuration space.
Previously, the address of a requested capability is define like that
"#define PCI_DCR 0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.
Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
1. Read Status register in PCIe configuration space to confirm that
Capabilities List is valid.
2. Find the address of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pci.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 749411c101..5be718b162 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -18,24 +18,6 @@ /* Freescale-specific PCI config registers */ #define FSL_PCI_PBFR 0x44 -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X -/* Currently only the PCIe capability is used, so hardcode the offset. - * if more capabilities need to be justified, the capability link method - * should be applied here - */ -#define FSL_PCIE_CAP_ID 0x70 -#define PCI_DCR 0x78 /* PCIe Device Control Register */ -#define PCI_DSR 0x7a /* PCIe Device Status Register */ -#define PCI_LSR 0x82 /* PCIe Link Status Register */ -#define PCI_LCR 0x80 /* PCIe Link Control Register */ -#else -#define FSL_PCIE_CAP_ID 0x4c -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#endif - #define FSL_PCIE_CFG_RDY 0x4b0 #define FSL_PROG_IF_AGENT 0x1 |