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| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-07-22 10:35:10 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-08-07 12:44:12 -0400 |
| commit | 102b0b11195ffe421f352d510c15fd6bb0e7c8f3 (patch) | |
| tree | a19c72056cff002035a2b7f73e4bb98cb2e6351f /arch | |
| parent | 7127151d538d878bd073ca6d6cca630a4b35b76f (diff) | |
| download | u-boot-102b0b11195ffe421f352d510c15fd6bb0e7c8f3.tar.gz u-boot-102b0b11195ffe421f352d510c15fd6bb0e7c8f3.tar.bz2 u-boot-102b0b11195ffe421f352d510c15fd6bb0e7c8f3.zip | |
arm: dts: change MT7629 to use spi-mem rather than qspi
The original mtk_qspi driver has been removed. We change MT7629 to use
newly added mtk-spimem driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/mt7629-rfb.dts | 18 | ||||
| -rw-r--r-- | arch/arm/dts/mt7629.dtsi | 14 |
2 files changed, 23 insertions, 9 deletions
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index 08c3b59222..0981f9b3b1 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -13,7 +13,7 @@ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; aliases { - spi0 = &qspi; + spi0 = &snfi; }; chosen { @@ -33,7 +33,14 @@ }; &pinctrl { - qspi_pins: qspi-pins { + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + snor_pins: snor-pins { mux { function = "flash"; groups = "spi_nor"; @@ -55,9 +62,10 @@ }; }; -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; +&snfi { + pinctrl-names = "default", "snfi"; + pinctrl-0 = <&snor_pins>; + pinctrl-1 = <&snfi_pins>; status = "okay"; spi-flash@0{ diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index ecbd29d7ae..8ff19162f0 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -215,10 +215,16 @@ status = "disabled"; }; - qspi: qspi@11014000 { - compatible = "mediatek,mt7629-qspi"; - reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; - reg-names = "reg_base", "mem_base"; + snfi: snfi@1100d000 { + compatible = "mediatek,mtk-snfi-spi"; + reg = <0x1100d000 0x2000>; + clocks = <&pericfg CLK_PERI_NFI_PD>, + <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, + <&topckgen CLK_TOP_NFI_INFRA_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, + <&topckgen CLK_TOP_UNIVPLL2_D8>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; |