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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-08-27 11:05:23 +0000 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-28 13:47:47 +0530 |
| commit | 00acf26044f320f71458f4bcf479fc88199489c7 (patch) | |
| tree | dee47e17565324f912954f9c6684b610b78685c8 /arch | |
| parent | 92e025c6e15be4eb0f045da423eba0f58d61305f (diff) | |
| download | u-boot-00acf26044f320f71458f4bcf479fc88199489c7.tar.gz u-boot-00acf26044f320f71458f4bcf479fc88199489c7.tar.bz2 u-boot-00acf26044f320f71458f4bcf479fc88199489c7.zip | |
MPC8548: dts: Added PCIe DT node
MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/dts/mpc8548-post.dtsi | 9 | ||||
| -rw-r--r-- | arch/powerpc/dts/mpc8548cds.dts | 6 | ||||
| -rw-r--r-- | arch/powerpc/dts/mpc8548cds_36b.dts | 6 |
3 files changed, 21 insertions, 0 deletions
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 5533a4b598..2206f2da9f 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -25,3 +25,12 @@ last-interrupt-source = <255>; }; }; + +&pcie { + compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts index cceea345c8..3b927bd265 100644 --- a/arch/powerpc/dts/mpc8548cds.dts +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -18,6 +18,12 @@ soc: soc8548@e0000000 { ranges = <0x0 0x0 0xe0000000 0x100000>; }; + + pcie: pcie@e000a000 { + reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts index faff35cc36..98d7c2410b 100644 --- a/arch/powerpc/dts/mpc8548cds_36b.dts +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -18,6 +18,12 @@ soc: soc8548@fe0000000 { ranges = <0x0 0xf 0xe0000000 0x100000>; }; + + pcie: pcie@fe000a000 { + reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "mpc8548-post.dtsi" |