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| author | Simon Glass <sjg@chromium.org> | 2020-09-22 12:45:10 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-09-25 11:27:17 +0800 |
| commit | f37979e7b75e1290e9756c3e964a85ef8b10c3c7 (patch) | |
| tree | 0c3d6f10e90c19e57f367cb6ab0327e65d59b883 /arch/x86/include | |
| parent | d2628984b7831b26d8f9ac25c966d6151df7a929 (diff) | |
| download | u-boot-f37979e7b75e1290e9756c3e964a85ef8b10c3c7.tar.gz u-boot-f37979e7b75e1290e9756c3e964a85ef8b10c3c7.tar.bz2 u-boot-f37979e7b75e1290e9756c3e964a85ef8b10c3c7.zip | |
x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.
Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/acpi_table.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7047ee6c77..1b7ff50951 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -47,6 +47,17 @@ u32 acpi_fill_csrt(u32 current); int acpi_write_hpet(struct acpi_ctx *ctx); /** + * acpi_write_dbg2_pci_uart() - Write out a DBG2 table + * + * @ctx: Current ACPI context + * @dev: Debug UART device to describe + * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS) + * @return 0 if OK, -ve on error + */ +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size); + +/** * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table * * @gnvs: Table to fill in |