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| author | Sean Anderson <seanga2@gmail.com> | 2020-06-24 06:41:17 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:21 +0800 |
| commit | 9472630337e7c4ac442066b5a752aaa8c3b4d4a6 (patch) | |
| tree | 15f2ed2668c54a0f7dc594d8a555890a817434f9 /arch/riscv | |
| parent | 309c79f3de4976854b0a80982bd7cb57bcb712d0 (diff) | |
| download | u-boot-9472630337e7c4ac442066b5a752aaa8c3b4d4a6.tar.gz u-boot-9472630337e7c4ac442066b5a752aaa8c3b4d4a6.tar.bz2 u-boot-9472630337e7c4ac442066b5a752aaa8c3b4d4a6.zip | |
riscv: Clear pending interrupts before enabling IPIs
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220e0c..f408e41ab9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,6 +65,8 @@ _start: #else li t0, SIE_SSIE #endif + /* Clear any pending IPIs */ + csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif |