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| author | Niklas Cassel <niklas.cassel@wdc.com> | 2022-03-01 10:35:42 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-03-15 17:43:11 +0800 |
| commit | 530f29cba55726a52d22adb762d4af41bf21bf02 (patch) | |
| tree | d2c0bde59e6ced1312a2c5b24db170dbff9b8f61 /arch/riscv | |
| parent | a6c86ec2d6acbb173414ced61fc9c75f80b622f6 (diff) | |
| download | u-boot-530f29cba55726a52d22adb762d4af41bf21bf02.tar.gz u-boot-530f29cba55726a52d22adb762d4af41bf21bf02.tar.bz2 u-boot-530f29cba55726a52d22adb762d4af41bf21bf02.zip | |
k210: dts: align plic node with Linux
The Linux PLIC interrupt-controller driver actually initializes the hart
context registers in the PLIC driver exactly in the same order as
specified in the interrupts-extended device tree property. See the device
tree binding [1].
The ordering of the interrupts is therefore essential in order to
configure the PLIC correctly.
Fix the order so that we will have sane IRQ behavior when booting Linux
with the u-boot device tree.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/k210.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index cf5c2360fb..3cc8379133 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -134,8 +134,8 @@ compatible = "canaan,k210-plic", "sifive,plic-1.0.0", "riscv,plic0"; reg = <0xC000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>, - <&cpu1_intc 9>, <&cpu1_intc 11>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; riscv,ndev = <65>; riscv,max-priority = <7>; }; |