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| author | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-05-28 20:49:57 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-05-30 16:01:09 +0800 |
| commit | cea0ed2e3f37a36e6243bed8c3491d2281c30287 (patch) | |
| tree | d31d21ebf1adffbefec27966a1ea8a417515713e /arch/riscv | |
| parent | ceec4761141a920602c4a4c7b90039d144ec2e58 (diff) | |
| download | u-boot-cea0ed2e3f37a36e6243bed8c3491d2281c30287.tar.gz u-boot-cea0ed2e3f37a36e6243bed8c3491d2281c30287.tar.bz2 u-boot-cea0ed2e3f37a36e6243bed8c3491d2281c30287.zip | |
riscv: remove cache enablement in start.S
Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a9e1935692..8e58f641f1 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -210,10 +210,6 @@ wait_for_gd_init: bnez s2, secondary_hart_loop #endif - /* Enable cache */ - jal icache_enable - jal dcache_enable - #ifdef CONFIG_DEBUG_UART jal debug_uart_init #endif |