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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2024-06-19 17:22:52 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-07-22 11:15:11 +0800 |
| commit | 36756308a215225e1a6421fc15e31780871059e4 (patch) | |
| tree | e4a03566b36de6b65ba587de2f4e39a317e48c8c /arch/riscv | |
| parent | 66b5ee9c558ea5a4360a9bfe0bf894098ff69f7e (diff) | |
| download | u-boot-36756308a215225e1a6421fc15e31780871059e4.tar.gz u-boot-36756308a215225e1a6421fc15e31780871059e4.tar.bz2 u-boot-36756308a215225e1a6421fc15e31780871059e4.zip | |
riscv: semihosting: correct alignment
Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
assembly file") reduced the alignment of function smh_trap().
As described in the "RISC-V Semihosting" specification [1] the ssli,
ebreak, and srai statements must all reside in the same memory page.
[1] RISC-V Semihosting, Version 0.4, 12th June 2024
https://github.com/riscv-non-isa/riscv-semihosting
Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/lib/semihosting.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/semihosting.S b/arch/riscv/lib/semihosting.S index c0c571bce9..49bb419a96 100644 --- a/arch/riscv/lib/semihosting.S +++ b/arch/riscv/lib/semihosting.S @@ -8,7 +8,7 @@ .pushsection .text.smh_trap, "ax" ENTRY(smh_trap) - .align 2 + .align 4 /* keep slli, ebreak, srai in same page */ .option push .option norvc /* semihosting sequence must be 32-bit wide */ |