diff options
| author | Zong Li <zong.li@sifive.com> | 2021-09-01 15:01:40 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-09-07 10:34:29 +0800 |
| commit | 4d4222d07432faffe3a0fe35c483e116a28eb217 (patch) | |
| tree | d231a09a9223c329f6b3dde902a43695e2c96e26 /arch/riscv/lib/cache.c | |
| parent | 43a21839285c1ba3b65534def898a2b5e2d46314 (diff) | |
| download | u-boot-4d4222d07432faffe3a0fe35c483e116a28eb217.tar.gz u-boot-4d4222d07432faffe3a0fe35c483e116a28eb217.tar.bz2 u-boot-4d4222d07432faffe3a0fe35c483e116a28eb217.zip | |
common: board_r: support enable_caches for RISC-V
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib/cache.c')
| -rw-r--r-- | arch/riscv/lib/cache.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..686e699efb 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,7 @@ __weak int dcache_status(void) { return 0; } + +__weak void enable_caches(void) +{ +} |