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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-02-06 16:10:47 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-17 19:07:48 +0800 |
| commit | d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5 (patch) | |
| tree | 57185976e0b05d9ccfe860e7602a6f94275343ed /arch/riscv/include/asm/arch-andes/csr.h | |
| parent | 51415fa634d2ff0e2d10eeefb739cdb941d19412 (diff) | |
| download | u-boot-d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5.tar.gz u-boot-d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5.tar.bz2 u-boot-d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5.zip | |
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/include/asm/arch-andes/csr.h')
| -rw-r--r-- | arch/riscv/include/asm/arch-andes/csr.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h new file mode 100644 index 0000000000..c7ed920cde --- /dev/null +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ + +#ifndef _ASM_ANDES_CSR_H +#define _ASM_ANDES_CSR_H + +#include <asm/asm.h> +#include <linux/const.h> + +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 +#define CSR_MCCTLCOMMAND 0x7cc + +#define MCACHE_CTL_IC_EN_OFFSET 0 +#define MCACHE_CTL_DC_EN_OFFSET 1 +#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define MCACHE_CTL_DC_COHEN_OFFSET 19 +#define MCACHE_CTL_DC_COHSTA_OFFSET 20 + +#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) +#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) +#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) +#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) +#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) + +#define CCTL_L1D_WBINVAL_ALL 6 + +#endif /* _ASM_ANDES_CSR_H */ |