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| author | Tianrui Wei <tianrui-wei@outlook.com> | 2021-07-01 12:54:19 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-07-06 13:50:56 +0800 |
| commit | 8a44fe69439438797b93b2e7dd70e1a8fad31519 (patch) | |
| tree | 327e92caeef61a85ca5c9fc1824673764736d59a /arch/riscv/dts/Makefile | |
| parent | fe01f41d57b79d9ca94604503a25e55175744d42 (diff) | |
| download | u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.tar.gz u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.tar.bz2 u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.zip | |
board: riscv: add openpiton-riscv64 SoC support
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/dts/Makefile')
| -rw-r--r-- | arch/riscv/dts/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 7778874831..b6e9166767 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb |