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authorThomas Chou <thomas@wytron.com.tw>2015-10-21 21:34:57 +0800
committerThomas Chou <thomas@wytron.com.tw>2015-10-23 07:37:03 +0800
commitbcae80e9551bc0ba2d67e78bda57b9283b4bab12 (patch)
tree200069cf225f838daaaaf8d5cb0958d5a0b164b5 /arch/nios2/cpu
parent88d5ecf4b9c0d5a3bff5d6d98ab7383a550a57db (diff)
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nios2: convert nios2 cpu to driver model
Convert nios2 cpu to driver model. The cpu parameters are extracted from device tree and saved to global data structure. We will use them to replace the custom_fpga.h . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/nios2/cpu')
-rw-r--r--arch/nios2/cpu/cpu.c90
1 files changed, 87 insertions, 3 deletions
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 39ae97221c..34eb7bd683 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -6,7 +6,9 @@
*/
#include <common.h>
-#include <asm/nios2.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,10 +53,92 @@ void dcache_disable(void)
flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
}
-int arch_cpu_init(void)
+int arch_cpu_init_dm(void)
{
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_CPU, &dev);
+ if (ret)
+ return ret;
+ if (!dev)
+ return -ENODEV;
+
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size)
+{
+ const char *cpu_name = "Nios-II";
+
+ if (size < strlen(cpu_name))
+ return -ENOSPC;
+ strcpy(buf, cpu_name);
+
+ return 0;
+}
+
+static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ info->cpu_freq = gd->cpu_clk;
+ info->features = (1 << CPU_FEAT_L1_CACHE) |
+ (gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
+
+ return 0;
+}
+
+static int altera_nios2_get_count(struct udevice *dev)
+{
+ return 1;
+}
+
+static int altera_nios2_probe(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ gd->cpu_clk = fdtdec_get_int(blob, node,
+ "clock-frequency", 0);
+ gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
+ "dcache-line-size", 0);
+ gd->arch.icache_line_size = fdtdec_get_int(blob, node,
+ "icache-line-size", 0);
+ gd->arch.dcache_size = fdtdec_get_int(blob, node,
+ "dcache-size", 0);
+ gd->arch.icache_size = fdtdec_get_int(blob, node,
+ "icache-size", 0);
+ gd->arch.reset_addr = fdtdec_get_int(blob, node,
+ "altr,reset-addr", 0);
+ gd->arch.exception_addr = fdtdec_get_int(blob, node,
+ "altr,exception-addr", 0);
+ gd->arch.has_initda = fdtdec_get_int(blob, node,
+ "altr,has-initda", 0);
+ gd->arch.has_mmu = fdtdec_get_int(blob, node,
+ "altr,has-mmu", 0);
+ gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
+
+ return 0;
+}
+
+static const struct cpu_ops altera_nios2_ops = {
+ .get_desc = altera_nios2_get_desc,
+ .get_info = altera_nios2_get_info,
+ .get_count = altera_nios2_get_count,
+};
+
+static const struct udevice_id altera_nios2_ids[] = {
+ { .compatible = "altr,nios2-1.0" },
+ { .compatible = "altr,nios2-1.1" },
+ { }
+};
+
+U_BOOT_DRIVER(altera_nios2) = {
+ .name = "altera_nios2",
+ .id = UCLASS_CPU,
+ .of_match = altera_nios2_ids,
+ .probe = altera_nios2_probe,
+ .ops = &altera_nios2_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};