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| author | Tom Rini <trini@konsulko.com> | 2024-03-19 09:10:30 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-19 09:10:30 -0400 |
| commit | f048104999db28d49362201eaebfc91adb14f47c (patch) | |
| tree | d8a909e13b846bb4a443283a3d948a39bb835995 /arch/mips | |
| parent | b145877c22b391a4872c875145a8f86f6ffebaba (diff) | |
| parent | 386fca68960994ece0d9da8a69a14495b5f1aedf (diff) | |
| download | u-boot-f048104999db28d49362201eaebfc91adb14f47c.tar.gz u-boot-f048104999db28d49362201eaebfc91adb14f47c.tar.bz2 u-boot-f048104999db28d49362201eaebfc91adb14f47c.zip | |
Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
- A new driver in the misc to register setting from device tree. This
also provides user a clean interface and all register settings are
centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
new files are created for board, dts, configs and makefile to create
the base for Agilex5.
Build-tested on SoC64 boards, boot tested on some of them.
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/lib/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/lib/cache_init.S | 4 | ||||
| -rw-r--r-- | arch/mips/lib/udivdi3.c | 17 |
3 files changed, 20 insertions, 3 deletions
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 9ee1fcb5c7..1621cc9a1f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -14,4 +14,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-$(CONFIG_SPL_BUILD) += spl.o -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 602741c65d..d64209d76a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -431,9 +431,9 @@ LEAF(change_k0_cca) #else xor a0, a0, t0 andi a0, a0, CONF_CM_CMASK - xor a0, a0, t0 + xor t0, a0, t0 #endif - mtc0 a0, CP0_CONFIG + mtc0 t0, CP0_CONFIG jr.hb ra END(change_k0_cca) diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c new file mode 100644 index 0000000000..4d780117cf --- /dev/null +++ b/arch/mips/lib/udivdi3.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "libgcc.h" + +#if BITS_PER_LONG == 32 + +#include <div64.h> + +long long __udivdi3(long long u, word_type b) +{ + long long ret = u; + + __div64_32(&ret, b); + return ret; +} + +#endif /* BITS_PER_LONG == 32 */ |