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| author | Lars Povlsen <lars.povlsen@microchip.com> | 2019-01-08 10:38:33 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-01-16 13:56:43 +0100 |
| commit | fd6e0b05252dd20579129d420442ef017287e89d (patch) | |
| tree | 99f8d86f6921eac2bf97d6a4b1402303db789f87 /arch/mips/mach-mscc | |
| parent | 82d5464788d3b7be8bd21d6472a0fa6959afaa2c (diff) | |
| download | u-boot-fd6e0b05252dd20579129d420442ef017287e89d.tar.gz u-boot-fd6e0b05252dd20579129d420442ef017287e89d.tar.bz2 u-boot-fd6e0b05252dd20579129d420442ef017287e89d.zip | |
mips: spi: mscc: Add fast bitbang SPI driver
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.
Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/mach-mscc')
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/common.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index d18ae78bfd..7765c060ed 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -29,6 +29,44 @@ /* Common utility functions */ +/* + * Perform a number of NOP instructions, blocks of 8 instructions. + * The (inlined) function will not affect cache or processor state. + */ +static inline void mscc_vcoreiii_nop_delay(int delay) +{ + while (delay > 0) { +#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;") + switch (delay) { + case 8: + DELAY_8_NOPS(); + /* fallthrough */ + case 7: + DELAY_8_NOPS(); + /* fallthrough */ + case 6: + DELAY_8_NOPS(); + /* fallthrough */ + case 5: + DELAY_8_NOPS(); + /* fallthrough */ + case 4: + DELAY_8_NOPS(); + /* fallthrough */ + case 3: + DELAY_8_NOPS(); + /* fallthrough */ + case 2: + DELAY_8_NOPS(); + /* fallthrough */ + case 1: + DELAY_8_NOPS(); + } + delay -= 8; +#undef DELAY_8_NOPS + } +} + int mscc_phy_rd_wr(u8 read, u32 miim_controller, u8 miim_addr, |