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author | Chris Packham <judge.packham@gmail.com> | 2022-11-05 17:24:00 +1300 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2022-11-07 07:46:28 +0100 |
commit | 6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a (patch) | |
tree | f5d23fbb3154e990063229e819c1b46dfb399241 /arch/arm | |
parent | 7d7bb99e22783cfee4ecd078d054fcc4cd2948cb (diff) | |
download | u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.tar.gz u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.tar.bz2 u-boot-6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a.zip |
arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/dts/ac5-98dx35xx-rd.dts | 129 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/Kconfig | 9 |
3 files changed, 139 insertions, 2 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 791838733c..b52077cddc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -278,7 +278,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9132-db-A.dtb \ cn9132-db-B.dtb \ cn9130-crb-A.dtb \ - cn9130-crb-B.dtb + cn9130-crb-B.dtb \ + ac5-98dx35xx-rd.dtb endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts new file mode 100644 index 0000000000..d9f217cd4a --- /dev/null +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For RD-AC5X. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "ac5-98dx35xx.dtsi" + +/ { + model = "Marvell RD-AC5X Board"; + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + spi0 = &spi0; + i2c0 = &i2c0; + i2c1 = &i2c1; + usb0 = &usb0; + usb1 = &usb1; + pinctrl0 = &pinctrl0; + sar-reg0 = "/config-space/sar-reg"; + }; + + usb1phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; +}; + +/* USB0 is a host USB */ +&usb0 { + status = "okay"; +}; + +/* USB1 is a peripheral USB */ +&usb1 { + status = "okay"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + +&spi0 { + status = "okay"; + + spiflash0: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&pinctrl0 { + /* + * MPP Bus: MPP# mode# + * eMMC [0-11] 0x1 + * SPI[0] [12-17] 0x1 + * TSEN_INT [18] 0x1 + * DEV_INIT [19] 0x1 + * SPI[1] [20-23] 0x3 + * UART[1] [24-25] 0x3 + * I2C[0] [26-27] 0x1 + * XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem + * SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem + * UART[0] [32-33] 0x1 + * OOB_SMI [34-35] 0x1 + * PTP_CLK0_OUT [36] 0x1 + * PTP_PULSE_OUT [37] 0x1 + * RCVR_CLK_OUT [38] 0x1 + * GPIO(in/out) [39] 0x0 + * GPIO(in/out) [40] 0x0 + * PTP_REF_CLK [41] 0x1 + * PTP_CLK0 [42] 0x1 + * LED0_CLK [43] 0x1 + * LED0_STB [44] 0x1 + * LED0_DATA [45] 0x1 + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 + 3 3 3 3 3 3 1 1 1 1 + 2 2 1 1 1 1 1 1 1 0 + 0 1 1 1 1 1 >; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index e2c98dffe2..594e9a03d9 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -98,7 +98,7 @@ config CUSTOMER_BOARD_SUPPORT bool choice - prompt "Armada XP/375/38x/3700/7K/8K board select" + prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select" optional config TARGET_CLEARFOG @@ -150,6 +150,10 @@ config TARGET_MVEBU_ARMADA_8K select BOARD_LATE_INIT imply SCSI +config TARGET_MVEBU_ALLEYCAT5 + bool "Support AlleyCat 5 platforms" + select ALLEYCAT_5 + config TARGET_OCTEONTX2_CN913x bool "Support CN913x platforms" select ARMADA_8K @@ -258,6 +262,7 @@ config SYS_BOARD default "x530" if TARGET_X530 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG @@ -278,6 +283,7 @@ config SYS_CONFIG_NAME default "x530" if TARGET_X530 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP @@ -297,6 +303,7 @@ config SYS_VENDOR default "gdsys" if TARGET_CONTROLCENTERDC default "alliedtelesis" if TARGET_X530 default "mikrotik" if TARGET_CRS3XX_98DX3236 + default "Marvell" if TARGET_MVEBU_ALLEYCAT5 config SYS_SOC default "mvebu" |