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author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2021-08-10 06:50:18 -0600 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2021-08-26 08:08:11 +0200 |
commit | a890a53ad2cdda973959947619245832203cd7f3 (patch) | |
tree | db049f78a71a604e881006e6252578038ed73be0 /arch/arm/mach-zynqmp | |
parent | 5e1a3be6674ba9945ad28291cb6d8e511db6eb92 (diff) | |
download | u-boot-a890a53ad2cdda973959947619245832203cd7f3.tar.gz u-boot-a890a53ad2cdda973959947619245832203cd7f3.tar.bz2 u-boot-a890a53ad2cdda973959947619245832203cd7f3.zip |
soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynqmp')
-rw-r--r-- | arch/arm/mach-zynqmp/cpu.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-zynqmp/include/mach/hardware.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 29743cae5a..26e285c24f 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <zynqmp_firmware.h> #include <asm/cache.h> +#include <dm/platdata.h> #define ZYNQ_SILICON_VER_MASK 0xF000 #define ZYNQ_SILICON_VER_SHIFT 12 @@ -218,3 +219,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) return ret; } + +U_BOOT_DRVINFO(soc_xilinx_zynqmp) = { + .name = "soc_xilinx_zynqmp", +}; diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 3776499070..eebf38551c 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -69,6 +69,9 @@ struct iou_scntr_secure { #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) +#define ZYNQMP_PS_VERSION 0xFFCA0044 +#define ZYNQMP_PS_VER_MASK GENMASK(1, 0) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F #define QSPI_MODE_24BIT 0x00000001 |