arm: meson: remove static ethernet link setup

The static ethernet link type config code is no more needed because now handled by
the meson8b glue driver, delete it.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

4 files changed, 0 insertions, 89 deletions

diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
index 91c87696e0..12042de935 100644
--- a/arch/arm/include/asm/arch-meson/axg.h
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -31,26 +31,4 @@
 #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT	16
 #define AXG_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
 
-/* Peripherals registers */
-#define AXG_PERIPHS_ADDR(off)	(AXG_PERIPHS_BASE + ((off) << 2))
-
-#define AXG_ETH_REG_0		AXG_PERIPHS_ADDR(0x50)
-#define AXG_ETH_REG_1		AXG_PERIPHS_ADDR(0x51)
-
-#define AXG_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
-#define AXG_ETH_REG_0_PHY_INTF_RMII	BIT(2)
-#define AXG_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
-#define AXG_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
-#define AXG_ETH_REG_0_PHY_CLK_EN	BIT(10)
-#define AXG_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
-#define AXG_ETH_REG_0_CLK_EN		BIT(12)
-
-/* HIU registers */
-#define AXG_HIU_ADDR(off)	(AXG_HIU_BASE + ((off) << 2))
-
-#define AXG_MEM_PD_REG_0	AXG_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define AXG_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
-
 #endif /* __AXG_H__ */
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index f765cd7c4c..c0070615c2 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -7,18 +7,6 @@
 #ifndef __MESON_ETH_H__
 #define __MESON_ETH_H__
 
-#include <phy.h>
-
-enum {
-	/* Use Internal RMII PHY */
-	MESON_USE_INTERNAL_RMII_PHY = 1,
-};
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags);
-
 /* Generate an unique MAC address based on the HW serial */
 int meson_generate_serial_ethaddr(void);
 
diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h
index db29cc3a00..ef4f301f7d 100644
--- a/arch/arm/include/asm/arch-meson/g12a.h
+++ b/arch/arm/include/asm/arch-meson/g12a.h
@@ -32,39 +32,4 @@
 #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT	16
 #define G12A_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
 
-/* Peripherals registers */
-#define G12A_PERIPHS_ADDR(off)	(G12A_PERIPHS_BASE + ((off) << 2))
-
-#define G12A_ETH_REG_0			G12A_PERIPHS_ADDR(0x50)
-#define G12A_ETH_REG_1			G12A_PERIPHS_ADDR(0x51)
-
-#define G12A_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
-#define G12A_ETH_REG_0_PHY_INTF_RMII	BIT(2)
-#define G12A_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
-#define G12A_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
-#define G12A_ETH_REG_0_PHY_CLK_EN	BIT(10)
-#define G12A_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
-#define G12A_ETH_REG_0_CLK_EN		BIT(12)
-
-#define G12A_ETH_PHY_ADDR(off)	(G12A_ETH_PHY_BASE + ((off) << 2))
-#define ETH_PLL_CNTL0			G12A_ETH_PHY_ADDR(0x11)
-#define ETH_PLL_CNTL1			G12A_ETH_PHY_ADDR(0x12)
-#define ETH_PLL_CNTL2			G12A_ETH_PHY_ADDR(0x13)
-#define ETH_PLL_CNTL3			G12A_ETH_PHY_ADDR(0x14)
-#define ETH_PLL_CNTL4			G12A_ETH_PHY_ADDR(0x15)
-#define ETH_PLL_CNTL5			G12A_ETH_PHY_ADDR(0x16)
-#define ETH_PLL_CNTL6			G12A_ETH_PHY_ADDR(0x17)
-#define ETH_PLL_CNTL7			G12A_ETH_PHY_ADDR(0x18)
-#define ETH_PHY_CNTL0			G12A_ETH_PHY_ADDR(0x20)
-#define ETH_PHY_CNTL1			G12A_ETH_PHY_ADDR(0x21)
-#define ETH_PHY_CNTL2			G12A_ETH_PHY_ADDR(0x22)
-
-/* HIU registers */
-#define G12A_HIU_ADDR(off)	(G12A_HIU_BASE + ((off) << 2))
-
-#define G12A_MEM_PD_REG_0		G12A_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define G12A_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
-
 #endif /* __G12A_H__ */
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
index 743d2e8bb9..26ec5d0bc3 100644
--- a/arch/arm/include/asm/arch-meson/gx.h
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -41,24 +41,4 @@
 #define GX_GPIO_IN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
 #define GX_GPIO_OUT(n)	GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
 
-#define GX_ETH_REG_0		GX_PERIPHS_ADDR(0x50)
-#define GX_ETH_REG_1		GX_PERIPHS_ADDR(0x51)
-#define GX_ETH_REG_2		GX_PERIPHS_ADDR(0x56)
-#define GX_ETH_REG_3		GX_PERIPHS_ADDR(0x57)
-
-#define GX_ETH_REG_0_PHY_INTF		BIT(0)
-#define GX_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
-#define GX_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
-#define GX_ETH_REG_0_PHY_CLK_EN	BIT(10)
-#define GX_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
-#define GX_ETH_REG_0_CLK_EN		BIT(12)
-
-/* HIU registers */
-#define GX_HIU_ADDR(off)	(GX_HIU_BASE + ((off) << 2))
-
-#define GX_MEM_PD_REG_0	GX_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define GX_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
-
 #endif /* __GX_H__ */