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| author | Heesub Shin <heesub@gmail.com> | 2024-04-28 23:24:02 +0900 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2024-06-18 08:55:52 +0200 |
| commit | 2ae44edf1d341db1a0102150e02f463c90d657a0 (patch) | |
| tree | bf0d2f8555e5e0f4e082ea29cb834d15f3c4ecf9 /arch/arm/dts | |
| parent | 69374aa86aa2fd6e301f7e4acfd2f3fb4441c68a (diff) | |
| download | u-boot-2ae44edf1d341db1a0102150e02f463c90d657a0.tar.gz u-boot-2ae44edf1d341db1a0102150e02f463c90d657a0.tar.bz2 u-boot-2ae44edf1d341db1a0102150e02f463c90d657a0.zip | |
ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; }; - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + cfg = < 3 124 5 9 9 PQR(1,1,1) >; bootph-all; }; }; |