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| author | Michal Simek <michal.simek@xilinx.com> | 2021-11-18 13:42:28 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2022-01-05 10:22:02 +0100 |
| commit | ca442169412ae74c1c45b4da5432bdbe74c6e890 (patch) | |
| tree | 284265ab71e88f9067a8daecb2279e0f377a8061 /arch/arm/dts/zynqmp.dtsi | |
| parent | 87b50f9aeaed91ebdcbb1375ea6523821e8b4510 (diff) | |
| download | u-boot-ca442169412ae74c1c45b4da5432bdbe74c6e890.tar.gz u-boot-ca442169412ae74c1c45b4da5432bdbe74c6e890.tar.bz2 u-boot-ca442169412ae74c1c45b4da5432bdbe74c6e890.zip | |
arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi
Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm/dts/zynqmp.dtsi')
| -rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 2264a80e33..015a582d7a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -527,7 +527,7 @@ interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -542,7 +542,7 @@ interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -557,7 +557,7 @@ interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; @@ -572,7 +572,7 @@ interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; |