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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-01-16 19:20:29 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-01-19 17:59:35 +0300 |
| commit | 19b10a42f6f89f49ce7f7f9c6e575c878f5fd1b7 (patch) | |
| tree | 4a5a7e0f8bc8ea301d2d9f7c243a87331438be4d /arch/arc/lib/cache.c | |
| parent | b0146f9e29ca2e82262416aca65395c322a618f9 (diff) | |
| download | u-boot-19b10a42f6f89f49ce7f7f9c6e575c878f5fd1b7.tar.gz u-boot-19b10a42f6f89f49ce7f7f9c6e575c878f5fd1b7.tar.bz2 u-boot-19b10a42f6f89f49ce7f7f9c6e575c878f5fd1b7.zip | |
ARC: Cache: Fix style violations reported by checkpatch
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/lib/cache.c')
| -rw-r--r-- | arch/arc/lib/cache.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d17948dbaf..04f1d9d59b 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -13,12 +13,12 @@ #include <asm/cache.h> /* Bit values in IC_CTRL */ -#define IC_CTRL_CACHE_DISABLE (1 << 0) +#define IC_CTRL_CACHE_DISABLE BIT(0) /* Bit values in DC_CTRL */ -#define DC_CTRL_CACHE_DISABLE (1 << 0) -#define DC_CTRL_INV_MODE_FLUSH (1 << 6) -#define DC_CTRL_FLUSH_STATUS (1 << 8) +#define DC_CTRL_CACHE_DISABLE BIT(0) +#define DC_CTRL_INV_MODE_FLUSH BIT(6) +#define DC_CTRL_FLUSH_STATUS BIT(8) #define CACHE_VER_NUM_MASK 0xF #define OP_INV 0x1 @@ -232,7 +232,7 @@ void read_decode_cache_bcr(void) } dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); - if (dbcr.fields.ver){ + if (dbcr.fields.ver) { dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) @@ -267,8 +267,7 @@ void cache_init(void) * so setting 0x11 implies 512M, 0x12 implies 1G... */ write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, - order_base_2(ap_size/1024) - 2); - + order_base_2(ap_size / 1024) - 2); /* IOC Aperture start must be aligned to the size of the aperture */ if (ap_base % ap_size != 0) @@ -277,7 +276,6 @@ void cache_init(void) write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); - } read_decode_mmu_bcr(); @@ -426,8 +424,7 @@ static unsigned int __before_dc_op(const int op) static void __after_dc_op(const int op, unsigned int reg) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ - while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) - ; + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); /* Switch back to default Invalidate mode */ if (op == OP_INV) @@ -453,6 +450,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { unsigned int ctrl_reg = __before_dc_op(cacheop); + __cache_line_loop(paddr, sz, cacheop); __after_dc_op(cacheop, ctrl_reg); } |