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| author | Masahisa Kojima <masahisa.kojima@linaro.org> | 2022-05-17 17:41:39 +0900 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-10 13:37:32 -0400 |
| commit | f81aaa0b33bec4292838e75d14a0653775aea45d (patch) | |
| tree | 5e5e53f7ec2e17ec8785f3dfd914b03638a44da2 | |
| parent | de9f2c9c2ed8ee4ffadc3909a46c17888fed619f (diff) | |
| download | u-boot-f81aaa0b33bec4292838e75d14a0653775aea45d.tar.gz u-boot-f81aaa0b33bec4292838e75d14a0653775aea45d.tar.bz2 u-boot-f81aaa0b33bec4292838e75d14a0653775aea45d.zip | |
spi: synquacer: simplify tx completion checking
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
| -rw-r--r-- | drivers/spi/spi-synquacer.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 5e1b3aedc7..0cae3dfc77 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -45,6 +45,7 @@ #define RXF 0x20 #define RXE 0x24 #define RXC 0x28 +#define TFES 1 #define TFLETE 4 #define TSSRS 6 #define RFMTE 5 @@ -345,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, if (priv->tx_words) { write_fifo(priv); } else { - u32 len; - - do { /* wait for shifter to empty out */ + /* wait for shifter to empty out */ + while (!(readl(priv->base + TXF) & BIT(TFES))) cpu_relax(); - len = readl(priv->base + DMSTATUS); - len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; - } while (tx_buf && len); + busy &= ~BIT(TXBIT); } } |