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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-05-24 10:29:58 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-08-11 16:43:41 -0400 |
| commit | d0e52c6f29efa9b728ed6e7f705d4e92a8ff9d2d (patch) | |
| tree | 34c612bb273d768935f3659b24aa13771d85057b | |
| parent | feb5a02f869d5678190dfc915ef6c2781b4f7a6c (diff) | |
| download | u-boot-d0e52c6f29efa9b728ed6e7f705d4e92a8ff9d2d.tar.gz u-boot-d0e52c6f29efa9b728ed6e7f705d4e92a8ff9d2d.tar.bz2 u-boot-d0e52c6f29efa9b728ed6e7f705d4e92a8ff9d2d.zip | |
pci: intel: Increase TLP polling counter
Some PCIe devices require longer time to response.
Increase polling counter to 20000 (~100ms).
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| -rw-r--r-- | drivers/pci/pcie_intel_fpga.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 3cdf05b314..e74b35ac16 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -56,7 +56,7 @@ #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) #define TLP_HDR_SIZE 3 -#define TLP_LOOP 500 +#define TLP_LOOP 20000 #define DWORD_MASK 3 #define IS_ROOT_PORT(pcie, bdf) \ |