board: hisilicon: Add support for Hikey960 board

This commit adds board support for Hikey960 board from Hisilicon. This
board is one of the Consumer Edition boards of the 96Boards family
powered by Kirin960 SoC.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/

The initial supported/tested devices include:
 - Debug serial
 - SD

With these support, it's good enough for loading Linux Kernel from SD.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

9 files changed, 612 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f0e301d41..be2c96a93d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1209,6 +1209,18 @@ config TARGET_HIKEY
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_HIKEY960
+	bool "Support HiKey960 96boards Consumer Edition Platform"
+	select ARM64
+	select DM
+	select DM_SERIAL
+	select OF_CONTROL
+	select PL01X_SERIAL
+	imply CMD_DM
+	  help
+	  Support for HiKey960 96boards platform. It features a HI3660
+	  SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
+
 config TARGET_POPLAR
 	bool "Support Poplar 96boards Enterprise Edition Platform"
 	select ARM64
@@ -1778,6 +1790,7 @@ source "board/grinn/chiliboard/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
+source "board/hisilicon/hikey960/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
 source "board/phytec/pcm051/Kconfig"
diff --git a/arch/arm/include/asm/arch-hi3660/hi3660.h b/arch/arm/include/asm/arch-hi3660/hi3660.h
new file mode 100644
index 0000000000..3ca0951543
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi3660/hi3660.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HI3660_H__
+#define __HI3660_H__
+
+#define HI3660_UART6_BASE			0xfff32000
+
+#define PMU_REG_BASE                            0xfff34000
+#define PMIC_HARDWARE_CTRL0                     (PMU_REG_BASE + (0x0C5 << 2))
+
+#define SCTRL_REG_BASE                          0xfff0a000
+#define SCTRL_SCFPLLCTRL0                       (SCTRL_REG_BASE + 0x120)
+#define SCTRL_SCFPLLCTRL0_FPLL0_EN              BIT(0)
+
+#define CRG_REG_BASE                            0xfff35000
+#define CRG_PEREN2                              (CRG_REG_BASE + 0x020)
+#define CRG_PERDIS2                             (CRG_REG_BASE + 0x024)
+#define CRG_PERCLKEN2                           (CRG_REG_BASE + 0x028)
+#define CRG_PERSTAT2                            (CRG_REG_BASE + 0x02C)
+#define CRG_PEREN4                              (CRG_REG_BASE + 0x040)
+#define CRG_PERDIS4                             (CRG_REG_BASE + 0x044)
+#define CRG_PERCLKEN4                           (CRG_REG_BASE + 0x048)
+#define CRG_PERSTAT4                            (CRG_REG_BASE + 0x04C)
+#define CRG_PERRSTEN2                           (CRG_REG_BASE + 0x078)
+#define CRG_PERRSTDIS2                          (CRG_REG_BASE + 0x07C)
+#define CRG_PERRSTSTAT2                         (CRG_REG_BASE + 0x080)
+#define CRG_PERRSTEN3                           (CRG_REG_BASE + 0x084)
+#define CRG_PERRSTDIS3                          (CRG_REG_BASE + 0x088)
+#define CRG_PERRSTSTAT3                         (CRG_REG_BASE + 0x08C)
+#define CRG_PERRSTEN4                           (CRG_REG_BASE + 0x090)
+#define CRG_PERRSTDIS4                          (CRG_REG_BASE + 0x094)
+#define CRG_PERRSTSTAT4                         (CRG_REG_BASE + 0x098)
+#define CRG_ISOEN                               (CRG_REG_BASE + 0x144)
+#define CRG_ISODIS                              (CRG_REG_BASE + 0x148)
+#define CRG_ISOSTAT                             (CRG_REG_BASE + 0x14C)
+
+#define PINMUX4_BASE				0xfff11000
+#define PINMUX4_SDDET				(PINMUX4_BASE + 0x60)
+
+#define PINCONF3_BASE				0xff37e800
+#define PINCONF3_SDCLK				(PINCONF3_BASE + 0x00)
+#define PINCONF3_SDCMD				(PINCONF3_BASE + 0x04)
+#define PINCONF3_SDDATA0			(PINCONF3_BASE + 0x08)
+#define PINCONF3_SDDATA1			(PINCONF3_BASE + 0x0c)
+#define PINCONF3_SDDATA2			(PINCONF3_BASE + 0x10)
+#define PINCONF3_SDDATA3			(PINCONF3_BASE + 0x14)
+
+#endif /*__HI3660_H__*/
diff --git a/board/hisilicon/hikey960/Kconfig b/board/hisilicon/hikey960/Kconfig
new file mode 100644
index 0000000000..89f096d649
--- /dev/null
+++ b/board/hisilicon/hikey960/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY960
+
+config SYS_BOARD
+	default "hikey960"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi3660"
+
+config SYS_CONFIG_NAME
+	default "hikey960"
+
+endif
diff --git a/board/hisilicon/hikey960/MAINTAINERS b/board/hisilicon/hikey960/MAINTAINERS
new file mode 100644
index 0000000000..2c98932163
--- /dev/null
+++ b/board/hisilicon/hikey960/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY960 BOARD
+M:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S:     Maintained
+F:     board/hisilicon/hikey960
+F:     include/configs/hikey960.h
+F:     configs/hikey960_defconfig
diff --git a/board/hisilicon/hikey960/Makefile b/board/hisilicon/hikey960/Makefile
new file mode 100644
index 0000000000..ea5a70921f
--- /dev/null
+++ b/board/hisilicon/hikey960/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y	:= hikey960.o
diff --git a/board/hisilicon/hikey960/README b/board/hisilicon/hikey960/README
new file mode 100644
index 0000000000..e1e330d535
--- /dev/null
+++ b/board/hisilicon/hikey960/README
@@ -0,0 +1,247 @@
+Introduction
+============
+
+HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
+The board/SoC has: -
+* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
+* ARM Mali G71 MP8 GPU
+* 3GB LPDDR4 SDRAM
+* 32GB UFS Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+More information about this board can be found in 96Boards website:
+https://www.96boards.org/product/hikey960/
+
+Currently the u-boot port supports: -
+* SD card
+
+Compile from source
+===================
+
+First get all the sources
+
+  > mkdir -p ~/hikey960/src ~/hikey960/bin
+  > cd ~/hikey960/src
+  > git clone https://github.com/ARM-software/arm-trusted-firmware
+  > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+  > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/config
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_usb_xloader.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_uce_boot.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/sec_xloader.img
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/recovery.bin
+  > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hikey_idt
+
+Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+  > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
+
+Compile U-Boot
+==============
+
+  > cd ~/hikey960/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/hikey960/bin/
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+  > cd ~/hikey960/src/arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+    SCP_BL2=~/hikey960/bin/lpm3.img \
+    BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
+
+Copy the resulting FIP binary
+  > cp build/hikey960/debug/fip.bin ~/hikey960/bin
+
+Compile l-loader
+================
+  > cd ~/hikey960/src/l-loader
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
+  > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
+  > ln -sf ~/hikey960/bin/u-boot.bin
+  > make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
+
+Copy the resulting binaries
+  > cp *.img ~/hikey960/bin
+  > cp l-loader.bin ~/hikey960/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
+
+Setup Console
+=============
+
+Install ser2net. Use telnet as the console since UEFI in recovery mode
+output window fails to display in minicom.
+
+  > sudo apt-get install ser2net
+
+Configure ser2net
+
+  > sudo vi /etc/ser2net.conf
+
+Append one line for serial-over-USB in #ser2net.conf
+
+  > 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+
+Start ser2net
+
+  > sudo killall ser2net
+  > sudo ser2net -u
+
+Open the console.
+
+  > telnet localhost 2004
+
+And you could open the console remotely, too.
+
+Flashing
+========
+
+1. Boot Hikey960 into recovery mode as per the below document:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
+
+Once Hikey960 is in recovery mode, flash the recovery binary:
+
+  > cd ~/hikey960/src
+  > chmod +x ./hikey_idt
+  > sudo ./hikey_idt -c config -p /dev/ttyUSB1
+
+Now move to the Hikey960 console and press `f` during UEFI boot. This
+will allow the board to boot into fastboot mode. Once the board is in
+fastboot mode, you should see the ID of the HiKey960 board using the
+following command
+
+  > sudo fastboot devices
+
+1ED3822A018E3372	fastboot
+
+3. Flash the images
+
+Now, the images can be flashed using fastboot:
+
+  > sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
+  > sudo fastboot flash xloader ~/hikey960/bin/sec_xloader.img
+  > sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
+  > sudo fastboot flash fip ~/hikey960/bin/fip.bin
+
+4. Set the "Boot Mode" switch to OFF position for normal boot mode.
+Then power on HiKey960
+
+Observe the console traces using UART6 on the Low Speed Expansion header:
+
+NOTICE:  BL2: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE:  BL2: Built : 18:15:58, Aug  2 2019
+INFO:    BL2: Doing platform setup
+INFO:    UFS LUN0 contains 1024 blocks with 4096-byte size
+INFO:    UFS LUN1 contains 1024 blocks with 4096-byte size
+INFO:    UFS LUN2 contains 2048 blocks with 4096-byte size
+INFO:    UFS LUN3 contains 7805952 blocks with 4096-byte size
+INFO:    ufs: change power mode success
+INFO:    BL2: Loading image id 2
+INFO:    Loading image id=2 at address 0x89c80000
+INFO:    Image id=2 loaded: 0x89c80000 - 0x89cb5088
+INFO:    BL2: Initiating SCP_BL2 transfer to SCP
+INFO:    BL2: SCP_BL2: 0x89c80000@0x35088
+INFO:    BL2: SCP_BL2 HEAD:
+INFO:    BL2: SCP_BL2 0x7000 0x179 0x159 0x149
+INFO:    BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x18f
+INFO:    BL2: SCP_BL2 0x191 0x0 0x193 0x195
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO:    BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
+INFO:    BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
+INFO:    BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
+INFO:    BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
+INFO:    BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
+INFO:    BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
+INFO:    BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
+INFO:    BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
+INFO:    BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
+INFO:    BL2: SCP_BL2 TAIL:
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO:    BL2: SCP_BL2 transferred to SCP
+INFO:    start fw loading
+INFO:    fw load success
+WARNING: BL2: Platform setup already done!!
+INFO:    BL2: Loading image id 3
+INFO:    Loading image id=3 at address 0x1ac58000
+INFO:    Image id=3 loaded: 0x1ac58000 - 0x1ac63024
+INFO:    BL2: Loading image id 5
+INFO:    Loading image id=5 at address 0x1ac98000
+INFO:    Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
+NOTICE:  BL2: Booting BL31
+INFO:    Entry point address = 0x1ac58000
+INFO:    SPSR = 0x3cd
+NOTICE:  BL31: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE:  BL31: Built : 18:16:01, Aug  2 2019
+INFO:    ARM GICv2 driver initialized
+INFO:    BL31: Initializing runtime services
+INFO:    BL31: cortex_a53: CPU workaround for 855873 was applied
+INFO:    plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
+INFO:    BL31: Preparing for EL3 exit to normal world
+INFO:    Entry point address = 0x1ac98000
+INFO:    SPSR = 0x3c9
+
+
+U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
+Hikey960
+
+DRAM:  3 GiB
+PSCI:  v1.1
+MMC:   dwmmc1@ff37f000: 0
+Loading Environment from EXT4... ** File not found /uboot.env **
+
+** Unable to read "/uboot.env" from mmc0:2 **
+In:    serial@fff32000
+Out:   serial@fff32000
+Err:   serial@fff32000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+switch to partitions #0, OK
+mmc0 is current device
+Scanning mmc 0:1...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+201 bytes read in 12 ms (15.6 KiB/s)
+1:      hikey960-kernel
+Retrieving file: /Image
+24689152 bytes read in 4377 ms (5.4 MiB/s)
+append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
+Retrieving file: /hi3660-hikey960.dtb
+35047 bytes read in 14 ms (2.4 MiB/s)
+## Flattened Device Tree blob at 10000000
+   Booting using the fdt blob at 0x10000000
+   Using Device Tree in place at 0000000010000000, end 000000001000b8e6
+
+Starting kernel ...
+
+[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
+[    0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
+[    0.000000] Machine model: HiKey960
+[    0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
+[    0.000000] printk: bootconsole [pl11] enabled
+[    0.000000] efi: Getting EFI parameters from FDT:
diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c
new file mode 100644
index 0000000000..eb9b99eaa9
--- /dev/null
+++ b/board/hisilicon/hikey960/hikey960.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/hi3660.h>
+#include <asm/armv8/mmu.h>
+#include <asm/psci.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+
+#define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
+#define PMIC_VSEL_MASK		0x7
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include <dm/platform_data/serial_pl01x.h>
+
+static const struct pl01x_serial_platdata serial_platdata = {
+	.base = HI3660_UART6_BASE,
+	.type = TYPE_PL011,
+	.clock = 19200000
+};
+
+U_BOOT_DEVICE(hikey960_serial0) = {
+	.name = "serial_pl01x",
+	.platdata = &serial_platdata,
+};
+#endif
+
+static struct mm_region hikey_mem_map[] = {
+	{
+		.virt = 0x0UL, /* DDR */
+		.phys = 0x0UL,
+		.size = 0xC0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xE0000000UL, /* Peripheral block */
+		.phys = 0xE0000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+void hikey960_sd_init(void)
+{
+	u32 data;
+
+	/* Enable FPLL0 */
+	data = readl(SCTRL_SCFPLLCTRL0);
+	data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
+	writel(data, SCTRL_SCFPLLCTRL0);
+
+	/* Configure LDO16 */
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
+		     PMIC_VSEL_MASK;
+	data |= 6;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
+
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+	data |= 2;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+
+	udelay(100);
+
+	/* Configure LDO9 */
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
+		     PMIC_VSEL_MASK;
+	data |= 5;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
+
+	data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+	data |= 2;
+	writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+
+	udelay(100);
+
+	/* GPIO CD */
+	writel(0, PINMUX4_SDDET);
+
+	/* SD Pinconf */
+	writel(15 << 4, PINCONF3_SDCLK);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
+	writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
+
+	/* Set SD clock mux */
+	do {
+		data = readl(CRG_REG_BASE + 0xb8);
+		data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
+		writel(data, CRG_REG_BASE + 0xb8);
+
+		data = readl(CRG_REG_BASE + 0xb8);
+	} while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
+
+	/* Take SD out of reset */
+	writel(1 << 18, CRG_PERRSTDIS4);
+	do {
+		data = readl(CRG_PERRSTSTAT4);
+	} while ((data & (1 << 18)) == (1 << 18));
+
+	/* Enable hclk_gate_sd */
+	data = readl(CRG_REG_BASE + 0);
+	data |= (1 << 30);
+	writel(data, CRG_REG_BASE + 0);
+
+	/* Enable clk_andgt_mmc */
+	data = readl(CRG_REG_BASE + 0xf4);
+	data |= ((1 << 3) | (1 << 3 << 16));
+	writel(data, CRG_REG_BASE + 0xf4);
+
+	/* Enable clk_gate_sd */
+	data = readl(CRG_PEREN4);
+	data |= (1 << 17);
+	writel(data, CRG_PEREN4);
+	do {
+		data = readl(CRG_PERCLKEN4);
+	} while ((data & (1 << 17)) != (1 << 17));
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	printf("PSCI:  v%ld.%ld\n",
+	       PSCI_VERSION_MAJOR(res.a0),
+		PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+	/* Init SD */
+	hikey960_sd_init();
+
+	show_psci_version();
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig
new file mode 100644
index 0000000000..6ed252f658
--- /dev/null
+++ b/configs/hikey960_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_TARGET_HIKEY960=y
+CONFIG_SYS_TEXT_BASE=0x1ac98000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_IDENT_STRING="\nHikey960"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="U-Boot => "
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
+CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_ENV_IS_IN_EXT4=y
+CONFIG_ENV_EXT4_INTERFACE="mmc"
+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
+CONFIG_ENV_EXT4_FILE="/uboot.env"
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
new file mode 100644
index 0000000000..f6f9c8d85a
--- /dev/null
+++ b/include/configs/hikey960.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+
+#define PHYS_SDRAM_1			0x00000000
+#define PHYS_SDRAM_1_SIZE		0xC0000000
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xe82b1000
+#define GICC_BASE			0xe82b2000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
+
+#define CONFIG_ENV_SIZE			0x1000
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"image=Image\0"	\
+				"fdtfile=hi3660-hikey960.dtb\0" \
+				"fdt_addr_r=0x10000000\0" \
+				"kernel_addr_r=0x11000000\0" \
+				"scriptaddr=0x00020000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+				BOOTENV
+
+#define CONFIG_ENV_SIZE			0x1000
+
+/* TODO: Remove this once the SD clock is fixed */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	1024
+
+#endif /* __HIKEY_H */