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| author | Karol Gugala <kgugala@antmicro.com> | 2015-07-23 14:33:01 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-08 16:26:19 +0200 |
| commit | ad008299712bbcaf822ebac0f4ab88069e1a1372 (patch) | |
| tree | ffcaf13bf1d1feb39342cfbe7102baba1e5b84eb | |
| parent | 38c4f8ba4c27fd0c7eb02fa1cdafc3e87e533573 (diff) | |
| download | u-boot-ad008299712bbcaf822ebac0f4ab88069e1a1372.tar.gz u-boot-ad008299712bbcaf822ebac0f4ab88069e1a1372.tar.bz2 u-boot-ad008299712bbcaf822ebac0f4ab88069e1a1372.zip | |
sunxi: nand: Add pinmux and clock settings for NAND support
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
| -rw-r--r-- | board/sunxi/board.c | 27 |
3 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 58aff1687a..01d3e28274 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -267,6 +267,8 @@ struct sunxi_ccm_reg { #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 #define CCM_MBUS_CTRL_GATE (0x1 << 31) +#define CCM_NAND_CTRL_ENABLE (0x1 << 31) + #define CCM_MMC_CTRL_M(x) ((x) - 1) #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) #define CCM_MMC_CTRL_N(x) ((x) << 16) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 8e67b3bcb8..8382101558 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -158,6 +158,7 @@ enum sunxi_gpio_number { #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 +#define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/board/sunxi/board.c b/board/sunxi/board.c index afed6a31ca..f85e825891 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -107,6 +107,28 @@ int dram_init(void) return 0; } +#if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +static void nand_pinmux_setup(void) +{ + unsigned int pin; + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + + for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +} + +static void nand_clock_setup(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); +} +#endif + #ifdef CONFIG_GENERIC_MMC static void mmc_pinmux_setup(int sdc) { @@ -431,6 +453,11 @@ void sunxi_board_init(void) power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); #endif +#ifdef CONFIG_SPL_NAND_SUNXI + nand_pinmux_setup(); + nand_clock_setup(); +#endif + printf("DRAM:"); ramsize = sunxi_dram_init(); printf(" %lu MiB\n", ramsize >> 20); |