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authorMichal Simek <michal.simek@amd.com>2024-01-29 08:46:43 +0100
committerMichal Simek <michal.simek@amd.com>2024-02-12 09:28:32 +0100
commit8e9566c98118fa66d663f65b13aa5577844224b8 (patch)
tree9dbb1613a75134141f6f7fc2f9b03871026229b9
parent0845f5c803f191db6992837da2faa1396861eaa4 (diff)
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arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
Describe 25Mhz fixed oscilator which is providing clock for PL based ethernet IPs. Physicially it is one chip but it is described as 2 fixed clock to be aligned with other SOM versions which were using integrated clock generators where clocks could be adjusted via i2c (si5332 chips). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com
-rw-r--r--arch/arm/dts/zynqmp-sck-kd-g-revA.dtso12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 766f78303e..b3fc17cbd5 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -32,6 +32,18 @@
#clock-cells = <0>;
clock-frequency = <26000000>;
};
+
+ clk_25_0: clock4 { /* u92/u91 - GEM2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_25_1: clock5 { /* u92/u91 - GEM3 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&can0 {