Merge branch 'master' of git://git.denx.de/u-boot-x86

93 files changed, 9859 insertions, 7530 deletions

diff --git a/Makefile b/Makefile
index 954a865381..4dc179b1d9 100644
--- a/Makefile
+++ b/Makefile
@@ -1452,6 +1452,7 @@ clean: $(clean-dirs)
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
+		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
 
 # mrproper - Delete all generated files, including .config
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 396023eee8..29d2307fa5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -274,6 +274,13 @@ config ENABLE_MRC_CACHE
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+	  For platforms that use Intel FSP for the memory initialization,
+	  please check FSP output HOB via U-Boot command 'fsp hob' to see
+	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+	  If such GUID does not exist, MRC cache is not avaiable on such
+	  platform (eg: Intel Queensbay), which means selecting this option
+	  here does not make any difference.
+
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	depends on !HAVE_FSP
@@ -439,21 +446,13 @@ config GENERATE_MP_TABLE
 config GENERATE_ACPI_TABLE
 	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 	default n
+	select QFW if QEMU
 	help
 	  The Advanced Configuration and Power Interface (ACPI) specification
 	  provides an open standard for device configuration and management
 	  by the operating system. It defines platform-independent interfaces
 	  for configuration and power management monitoring.
 
-config QEMU_ACPI_TABLE
-	bool "Load ACPI table from QEMU fw_cfg interface"
-	depends on GENERATE_ACPI_TABLE && QEMU
-	default y
-	help
-	  By default, U-Boot generates its own ACPI tables. This option, if
-	  enabled, disables U-Boot's version and loads ACPI tables generated
-	  by QEMU.
-
 config GENERATE_SMBIOS_TABLE
 	bool "Generate an SMBIOS (System Management BIOS) table"
 	default y
@@ -465,6 +464,22 @@ config GENERATE_SMBIOS_TABLE
 
 	  Check http://www.dmtf.org/standards/smbios for details.
 
+config SMBIOS_MANUFACTURER
+	string "SMBIOS Manufacturer"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_VENDOR
+	help
+	  The board manufacturer to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+	string "SMBIOS Product Name"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_BOARD
+	help
+	  The product name to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_BOARD).
+
 endmenu
 
 config MAX_PIRQ_LINKS
@@ -539,6 +554,20 @@ config SEABIOS
 
 	  Check http://www.seabios.org/SeaBIOS for details.
 
+config HIGH_TABLE_SIZE
+	hex "Size of configuration tables which reside in high memory"
+	default 0x10000
+	depends on SEABIOS
+	help
+	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+	  puts a copy of configuration tables in high memory region which
+	  is reserved on the stack before relocation. The region size is
+	  determined by this option.
+
+	  Increse it if the default size does not fit the board's needs.
+	  This is most likely due to a large ACPI DSDT table is used.
+
 source "arch/x86/lib/efi/Kconfig"
 
 endmenu
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 5be5491643..a0216f3059 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += early_uart.o
 obj-y += fsp_configs.o
 obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
new file mode 100644
index 0000000000..1d54f7dba1
--- /dev/null
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			2, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 25382f9aab..b31f24e262 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -53,14 +53,6 @@ int arch_misc_init(void)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
 #endif
 
 void reset_cpu(ulong addr)
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index f0798a7f9e..317f57d3f9 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -109,7 +109,8 @@ static void pch_enable_ioapic(void)
 {
 	u32 reg32;
 
-	io_apic_set_id(0x02);
+	/* Make sure this is a unique ID within system */
+	io_apic_set_id(0x04);
 
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(0x01);
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 4bf5d15b26..e7befde6ad 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 int dram_init(void)
 {
 	struct pei_data _pei_data __aligned(8);
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 845f86a176..1b042037bb 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,15 +39,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
-	return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -79,6 +71,16 @@ void board_final_cleanup(void)
 	}
 }
 
+int last_stage_init(void)
+{
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
+	board_final_cleanup();
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 233a6c8695..e522ff3b7f 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,10 +25,12 @@
 #include <errno.h>
 #include <malloc.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
+#include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
@@ -661,10 +663,20 @@ void show_boot_progress(int val)
 }
 
 #ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	write_tables();
 
+	board_final_cleanup();
+
 	return 0;
 }
 #endif
@@ -741,3 +753,18 @@ int cpu_init_r(void)
 
 	return 0;
 }
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+	high_table_reserve();
+#endif
+
+	return 0;
+}
+#endif
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 10dc4d47f0..dd2819a12c 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -15,14 +15,14 @@
 #include <dm.h>
 #include <asm/cache.h>
 #include <asm/control_regs.h>
+#include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/processor.h>
 #include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -266,6 +266,8 @@ int interrupt_init(void)
 	i8259_init();
 #endif
 
+	lapic_setup();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 2950783055..df3cd0abc7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +122,11 @@ static int create_pirq_routing_table(struct udevice *dev)
 	priv->irq_mask = fdtdec_get_int(blob, node,
 					"intel,pirq-mask", PIRQ_BITMAP);
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve IRQ9 for SCI */
+		priv->irq_mask &= ~(1 << 9);
+	}
+
 	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
@@ -142,6 +148,9 @@ static int create_pirq_routing_table(struct udevice *dev)
 		priv->ibase &= ~0xf;
 	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 	if (!cell || len % sizeof(struct pirq_routing))
 		return -EINVAL;
@@ -206,11 +215,30 @@ static int create_pirq_routing_table(struct udevice *dev)
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+	/* Fix up the table checksum */
+	rt->checksum = table_compute_checksum(rt, rt->size);
+
 	pirq_routing_table = rt;
 
 	return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
 	int ret;
@@ -224,6 +252,9 @@ int irq_router_common_init(struct udevice *dev)
 	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		irq_enable_sci(dev);
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 88ab7973fd..ff1faa5014 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <rtc.h>
 #include <pci.h>
-#include <asm/acpi.h>
 #include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index cef425669c..38e244b05e 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,10 +12,8 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
@@ -419,7 +417,6 @@ static int model_206ax_init(struct udevice *dev)
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index f7e0bc3f18..491f2894f9 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/msr.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e35e543c3e..9d9f63d70c 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -201,11 +201,6 @@ static int recovery_mode_enabled(void)
 	return false;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
 	const void *data;
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d23130eb..fbea2d1572 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v)
 
 void enable_lapic(void)
 {
-	msr_t msr;
-
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.hi &= 0xffffff00;
-	msr.lo |= MSR_IA32_APICBASE_ENABLE;
-	msr.lo &= ~MSR_IA32_APICBASE_BASE;
-	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(MSR_IA32_APICBASE, msr);
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
+
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.hi &= 0xffffff00;
+		msr.lo |= MSR_IA32_APICBASE_ENABLE;
+		msr.lo &= ~MSR_IA32_APICBASE_BASE;
+		msr.lo |= LAPIC_DEFAULT_BASE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 void disable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 unsigned long lapicid(void)
@@ -120,7 +124,6 @@ int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 
 void lapic_setup(void)
 {
-#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
@@ -150,11 +153,7 @@ void lapic_setup(void)
 		    LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
-	/* Only Pentium Pro and later have those MSR stuff */
-	debug("Disabling local apic: ");
-	disable_lapic();
-#endif /* CONFIG_SMP */
+
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2604a687ab..2b6b3bd04e 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
@@ -21,7 +22,6 @@
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/sipi.h>
-#include <asm/fw_cfg.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 #include <dm/lists.h>
@@ -408,8 +408,6 @@ static int init_bsp(struct udevice **devp)
 	cpu_get_name(processor_name);
 	debug("CPU: %s\n", processor_name);
 
-	lapic_setup();
-
 	apic_id = lapicid();
 	ret = find_cpu_by_apic_id(apic_id, devp);
 	if (ret) {
@@ -420,7 +418,7 @@ static int init_bsp(struct udevice **devp)
 	return 0;
 }
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 static int qemu_cpu_fixup(void)
 {
 	int ret;
@@ -496,7 +494,7 @@ int mp_init(struct mp_params *p)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 	ret = qemu_cpu_fixup();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 6eeddf154e..a080c5e2f4 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,4 +7,5 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index a1b70c6bde..b1a965e715 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,8 +8,8 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
+#include <qfw.h>
 #include <asm/cpu.h>
-#include <asm/fw_cfg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
new file mode 100644
index 0000000000..63853e4b22
--- /dev/null
+++ b/arch/x86/cpu/qemu/e820.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7ad0ee49a1..680e558ee8 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,15 +6,59 @@
 
 #include <common.h>
 #include <pci.h>
+#include <qfw.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
 #include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
 
 static bool i440fx;
 
+#ifdef CONFIG_QFW
+
+/* on x86, the qfw registers are all IO ports */
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 *
+	 * Note: on platform where the control register is IO port, the
+	 * endianness is little endian.
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+	/* the endianness of data register is string-preserving */
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+	/* the DMA address register is big endian */
+	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -88,7 +132,9 @@ static void qemu_chipset_init(void)
 		enable_pm_ich9();
 	}
 
-	qemu_fwcfg_init();
+#ifdef CONFIG_QFW
+	qemu_fwcfg_init(&fwcfg_x86_ops);
+#endif
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index afb3463797..bdd360a99f 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/ioapic.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -338,6 +339,9 @@ int arch_misc_init(void)
 	mrccache_save();
 #endif
 
+	/* Assign a unique I/O APIC ID */
+	io_apic_set_id(1);
+
 	return 0;
 }
 
@@ -360,12 +364,3 @@ void board_final_cleanup(void)
 
 	return;
 }
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4ea9262251..4a50d8665e 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -84,6 +84,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -249,10 +250,10 @@
 #include "microcode/m0230671117.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 478dece1ae..1a4ecaad0e 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -88,6 +88,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -269,10 +270,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 };
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 337513be57..78a1ef415c 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -154,6 +154,7 @@
 			irq-router {
 				compatible = "intel,queensbay-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xcee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 21c36412e2..da3cbff5cb 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -29,6 +29,18 @@
 		stdout-path = &pciuart0;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+	};
+
 	tsc-timer {
 		clock-frequency = <400000000>;
 	};
@@ -88,6 +100,7 @@
 			irq-router {
 				compatible = "intel,quark-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xdef8>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
deleted file mode 100644
index 90bf2fb712..0000000000
--- a/arch/x86/dts/microcode/m0130673322.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x322>;
-intel,date-code = <0x4012014>;
-intel,processor-signature = <0x30673>;
-intel,checksum = <0x17b0d914>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x22030000	0x14200104	0x73060300
-	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x22030000
-	0x00000000	0x00000000	0x31031420	0x11320000
-	0x01000000	0x73060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
-	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
-	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
-	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
-	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
-	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
-	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
-	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
-	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
-	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
-	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
-	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
-	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
-	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
-	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
-	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
-	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
-	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
-	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
-	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
-	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
-	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
-	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
-	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
-	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
-	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
-	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
-	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
-	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
-	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
-	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
-	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
-	0x8d03a7da	0x2e1d7c49	0x01ac68ae	0x93188770
-	0x0609e769	0x982ed28d	0xe40999e0	0x8932ebab
-	0x5637ad5a	0x2725e8ad	0x56d7caaf	0xc351faa2
-	0x09dbd737	0x0d2f3bf0	0x0623330d	0xdd547489
-	0xcca7e722	0xa9096d13	0x95b17818	0xc092cb81
-	0x72c6eefc	0x1811c37e	0x78161497	0x8be0c4c6
-	0xd63aeb19	0x91ab68df	0x8f2e5e4d	0xf4c74566
-	0x7677a553	0x19698ac3	0xedca0620	0x77f32470
-	0x031e011b	0x751f6696	0xb277d06e	0x3eae2742
-	0x133e621a	0x38fa3172	0x9398cc1c	0xf42a507b
-	0x4547d933	0x63a91eb0	0xf5bcf6a4	0x926ba056
-	0x0adf5bce	0x140f53e4	0x7ff6bb5c	0x87dd79ba
-	0xbba240ac	0x694f743d	0x709cdb20	0x5b4d4401
-	0xc9693610	0x55f9f268	0x1142bc3f	0xf8fe3689
-	0x04a93c4c	0x33dedc46	0xdc73c725	0x2f5ba264
-	0x5b7a6a69	0x024b64f5	0x6e8bfa12	0x62bf2aa7
-	0x520f5a07	0x3c7c4292	0xb7ad2613	0x1f78fc87
-	0xd5284e4e	0x2c730f33	0x8861e947	0x8bacef7d
-	0xbafa2608	0x14ed0b5b	0x3b9bfb02	0x24ced271
-	0x002b2941	0x22d4431c	0x855f4248	0x5ec46e29
-	0x6f1f42fb	0x5dd24fe0	0x290961f6	0xf392dbaf
-	0xa1a8d9c2	0x61e18f4e	0xfda59a70	0x5498daa5
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-	0xc4fd7512	0x6d43cd2f	0xcae99e08	0x453175ae
-	0xc6ee93a3	0x2fed0eac	0xe48fb73d	0x0afe2d2a
-	0x5966735e	0xdc7e5fb6	0xed1ef13d	0x7e08a106
-	0xd3ca0e6b	0x4ce5ca02	0xa0beebed	0xe982c609
-	0x1ee9e5a2	0x24ae26cb	0xfd4c08d4	0x5e85e850
-	0x11b54b3b	0x87209692	0x4a5b0c35	0xcd25dd6f
-	0xd9570253	0xaad0b9fe	0xaf984fee	0x6cf7ae2d
-	0x45d9926c	0x07a66ac6	0x8e7aacdc	0xaf587d66
-	0x53972a4e	0x8da4a6c9	0x2bc311e5	0x36938ae8
-	0x179b965d	0x515743f7	0xb5bbbdcd	0xd8602715
-	0x9e43049f	0x4e78a080	0xba3f1750	0x68635cf0
-	0x85823047	0xbb03b5fd	0xb0d747c8	0x58d214af
-	0x94b1ba85	0x6d2cf8ac	0x2bc1faeb	0x6bd7c1e3
-	0x127658e9	0x8b499020	0xab8f0f62	0xee665a6a
-	0x89240e4d	0x8a95342b	0x00b38ccc	0xe6b14d9d
-	0x32a2af71	0x4c9ecb69	0xc8de2685	0xd7385184
-	0x8e943872	0x809b2c79	0x108511da	0x08b4f54d
-	0x95f52442	0x26fe296f	0xf7e037c0	0xa1aecdd3
-	0x89774a91	0xde67c55f	0x1f9816dc	0x1469a4c2
-	0x28240be2	0x5fd0ad14	0x0949db3a	0x451b94d3
-	0x637e6d49	0x8a4771c8	0xf65104b7	0xc3058c40
-	0x592fe4d0	0xe26129f0	0xe66e6ce9	0x26ab39b8
-	0x308da532	0x205afe77	0x6dc78664	0x84d4890f
-	0x9d49fcb0	0xcac8f2ed	0xe713d798	0xfed7c75b
-	0xe441a0d4	0xdf60df37	0xc2eed2f5	0x2d68b20e
-	0x7827c89a	0x9d4cb9f2	0xb8912cce	0x07516335
-	0x976ffbb6	0x5cd0de48	0xed716f54	0x6f3c9f7f
-	0x34cf42d1	0xc1027cbb	0xde67c065	0xe0a229af
-	0xfc8bd2e8	0xd62ca176	0x8bfb76b2	0x54a1388f
-	0xe0650bb6	0x6d60682b	0xe16cf130	0xbd7c3ca2
-	0xea642814	0xa25f4d44	0x27013786	0x7316aa38
-	0x571511c8	0xf1b6b789	0xb7bfe72b	0x8fd2652c
-	0xbfc7771a	0x51a2e551	0x3bd738c2	0x2698b495
-	0xec69a196	0xd5ecb5c4	0x9bd3224c	0x6d9ab4cf
-	0x326c9942	0x4d711191	0xde9be50a	0xa980ca0b
-	0xe8e59dd0	0x4439e4ae	0x35de914d	0xee499a84
-	0xd1ca0c9d	0xfe6ee96d	0x5b1f4fd0	0xabf0621a
-	0x0c8220c7	0xcb6dbb1e	0xa5116036	0xe858d3c3
-	0x728e3a56	0x3b33e818	0xbe2643c1	0x497bbcc7
-	0xeb369828	0x9a4a01be	0x8c7e72a6	0xaf052f25
-	0x8d3ca85b	0x4703e55e	0x45647d4c	0x86d1e3e8
-	0x40ab59f9	0x3259b195	0xf979a147	0xb8961870
-	0x88b024f9	0x366e26bc	0xd6811525	0x252910c2
-	0x4223a20e	0x7fc971a3	0x4a639bf3	0xb6550c3b
-	0xfe05e552	0xbdc98897	0x509923ff	0xf51a5abc
-	0xc6cc0891	0x61cdac05	0x03a68664	0x1b80cc76
-	0xe18d8ee1	0x798bb4d2	0xd7769bf9	0x9ab4c02d
-	0x7484774b	0xa9ee2c8b	0x87d34c85	0x15697682
-	0x9f6a4a55	0x9d7a731c	0x10014d6a	0xb9798070
-	0xd42f79cb	0x89db59b3	0xd5b0a0b6	0xf60864a5
-	0x2d6fb084	0x1cb607b2	0x48232701	0x9310cbc6
-	0x5bc81c98	0x6b25016c	0x2014b99d	0x0836e60b
-	0x0addbc4c	0x3b8bac7c	0x8d95ac77	0x1d56c3c7
-	0x58333104	0x3d6eb719	0x676eb951	0xd5c2d1a3
-	0x239dae86	0x92181ab8	0xbdde9741	0x7995d452
-	0xe0020661	0x2f80c8b7	0xeedcd4fc	0xe4bde175
-	0xb98fdf78	0x84b9228f	0x78ecb4f3	0xe99e5d46
-	0xa33b9b96	0xe2cbc71c	0xc19e2146	0xdc0ee758
-	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
-	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
-	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
-	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
-	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
-	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
-	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
-	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
-	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
-	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
-	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
-	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
-	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
-	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
-	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
-	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
-	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
-	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
-	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
-	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
-	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
-	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
-	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
-	>;
diff --git a/arch/x86/dts/microcode/m0130673325.dtsi b/arch/x86/dts/microcode/m0130673325.dtsi
new file mode 100644
index 0000000000..8063a752c9
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673325.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x325>;
+intel,date-code = <0x11192014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x5edcd570>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x25030000	0x14201911	0x73060300
+	0x70d5dc5e	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x25030000
+	0x00000000	0x00000000	0x19111420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0xfff634fa	0x937ca2ab	0xb28d19b6	0xdefc54a7
+	0xd8df0b32	0x13e9a2a8	0x7b7cb24d	0xd588d3a7
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x1f504653	0xe21b5652	0xe97686b4
+	0x5f67c59f	0xa9b26fd4	0x9dc84f1a	0x0f02451e
+	0x0a821675	0x12547714	0xefe1084e	0x91260f23
+	0x17e46cf5	0x3dad6dd8	0x4e16210b	0x0472bd56
+	0xd3fca8a6	0xfa3f5184	0x87d91976	0xa7b008eb
+	0x17bad553	0x89835b41	0x32e7d87c	0xdfcf298a
+	0x6a740196	0x0405a296	0x4f830df5	0xfcf047f1
+	0xca0e7a10	0x8d0afa7b	0x08facdae	0xcf7bbe22
+	0x8e08e283	0x6b51333b	0x452cf734	0x03da5390
+	0x7075365b	0x402e71ba	0x4a8d4547	0x0da62d39
+	0x3fcae342	0xe8cb1437	0x6ddc21bd	0xe22b5edb
+	0x319decc1	0x6c558ad3	0x3b44648a	0x8cdf8642
+	0x5a3a8cdf	0x6aae06b2	0x7360d1a5	0x774351c9
+	0x88681d42	0x466d3573	0x6d8538cb	0xa3350f1e
+	0x7b431d3c	0x21074f32	0x6955a68f	0xa3988611
+	0xad1c79d3	0xe00884c6	0x12e5baa8	0x7dad4109
+	0x61d16a48	0xd2074a23	0x58611da6	0xad7b774e
+	0x90a80987	0x05aca95d	0x482b51ca	0xbb8fe27d
+	0x2abe5e48	0x590c8b98	0xef745dbf	0xce17a591
+	0x6607216b	0xbefec476	0x7a8b08a9	0xb281bfc4
+	0x76f7dc81	0xaacd78a8	0x38cd6888	0x9636aa2e
+	0x7035053d	0x069305f5	0x0da92823	0x46d344df
+	0xce46f308	0x1fcca5d0	0xf4b0daa0	0xed8ecd8e
+	0xdae9e33d	0x69be5bef	0xc545c95b	0xadeaeeb8
+	0xdd903783	0x5a2f3287	0x73865fd0	0x865d709d
+	0x1ed58537	0xe44c821a	0xc9ad0d97	0xe81b9851
+	0x552cf1e7	0x03a3b2dc	0x219194a0	0xd8875c82
+	0xe39b25b7	0x61149b84	0x79a99812	0x287eada3
+	0x057cc940	0x0ed85405	0xf4cbb20d	0x8d87a099
+	0x2018b6ae	0xd14f3646	0x35bf5bd8	0x82931be1
+	0x52234bd1	0x9143a967	0xd9d1a3d4	0x869c266c
+	0xcaff55f0	0x64ad39c2	0x02435da4	0x32e2907c
+	0xbc2682a9	0x60863cea	0x163028c0	0x007fc9fd
+	0x6553eb56	0xab00c11c	0x3aa77e22	0x87f722d4
+	0x004850a6	0x5460e040	0x9e91042c	0x46dd43c7
+	0x3b05c92f	0x060ce074	0x62730a12	0xc6d47872
+	0x03d26f06	0xf7b3d04f	0x92adc672	0xc31d8130
+	0xd40eab22	0x616b7f8f	0x56b2c742	0xde6015c3
+	0xc10c0d02	0x3ab28f97	0xa091494f	0x1fa0c28b
+	0xc76c5661	0x27effd8f	0x3de80c1e	0x5713a42c
+	0xd9114db2	0x17ab3314	0x0e3aea42	0x60712f1f
+	0x4a7d4389	0x9db1857c	0x1103baa8	0x579462a6
+	0x82ac5a7e	0xda8d9f67	0x835bed5a	0x08705479
+	0xbf4bd494	0x082d8b22	0x408878b0	0xa698e9d8
+	0x27fba6da	0x2308fb71	0xcc1b9c9c	0x5200bd18
+	0xf1baf601	0xe67b1d1b	0xf3c95153	0xf8fb4f22
+	0x2859e330	0x3e7bc864	0x02c88201	0xf835c5f7
+	0xcefd31e1	0x4c430b43	0xce13d99c	0xf9aa01ab
+	0x9f5c0d3a	0xbf06696f	0xc834c22c	0x145cf026
+	0xb45e1f1b	0x97302dd5	0x5b5d108a	0xffde5401
+	0xffbd2caf	0x8eb5c823	0x3f113711	0x144ec354
+	0xab3864a7	0xeee70354	0x208ea79c	0x1b2c7364
+	0xc3cb82d0	0x21d9b3bc	0x27846121	0x50bd8910
+	0x43a2616a	0xface9686	0xe12195b9	0xde4639d9
+	0x0b88b493	0x32b1685e	0xbd782bea	0xc674188e
+	0x23425d26	0x9d2d3c81	0x33b3a260	0x4ebebf2f
+	0x6a634d1f	0xb977b1c1	0x476223c5	0x654c5461
+	0xbeaa9c98	0x75242b30	0x26061148	0x69889154
+	0x910a2132	0x07df3136	0x372a7cf0	0x58541d8f
+	0x65ce78aa	0x0c6e4ff7	0xab8c31b6	0xbe39960d
+	0x63bc072d	0x53872b7c	0x959f3049	0xc13ba7a0
+	0xd7111cd7	0x5e68763f	0x923dc674	0xdb2e8a4d
+	0x5c2cd5e0	0xd93be0e2	0x1bccff32	0xbbdffc8a
+	0x1641ff1b	0xeab24fc7	0x70aff37e	0xc87fe4f8
+	0x32afd630	0x060dbdf9	0x6e119a8c	0x987e51c5
+	0x57abb8f6	0x15b3755b	0x938f709a	0x7c4b5522
+	0xfd376691	0xd909457d	0x58656778	0x3bdee518
+	0xaf65afd2	0xe1cd74ec	0xd2bc8a3a	0x9aa30f8b
+	0x6e1f183f	0xc2fa7bf8	0xa60385fd	0xe0320d46
+	0x2e5bc0df	0xf95b8c37	0xfa760bc7	0xc8960509
+	0xdebed2f2	0x560ac9de	0xb3ac0e62	0xefe328dc
+	0x358d5330	0x72c31526	0x5932780a	0xb3b824b4
+	0xda37daae	0x69dd74c1	0x41c91b5c	0x8180b956
+	0xc69574b5	0x1830993b	0x0d5ef14b	0xa8dec45f
+	0x5c4019ed	0x559e7b51	0xd07a3c14	0x49208a2b
+	0x5265dad8	0x1b9826c0	0xb8cc3edf	0x63ccaf33
+	0xdfdfb78b	0x3292f976	0x9f1ddbc1	0x2e3bfa8f
+	0xc4b5a941	0xd8b1fcea	0x68764a2c	0xbec828e1
+	0x07db4118	0x2022cfd1	0x6be82389	0x7ecb046a
+	0xd31a639f	0xa0f50a18	0xbb4dc035	0x765a6e5f
+	0x59fe51c8	0xd2138643	0xccfeebae	0x234c0440
+	0x49bcdabd	0x88e86cb6	0x48760e88	0xcc34f20c
+	0x0977dead	0xf3f0d324	0x736f4df6	0x0a94f658
+	0x0bbb01cb	0xe962549c	0x6a1c39c6	0xbec25a26
+	0x4cb71dd7	0xf1043105	0xba0f3726	0xc97645e3
+	0x23d4b508	0x7c0827ae	0x097f96f0	0x0a054e0a
+	0x79e7a543	0xbedbd7d1	0x52d2b51f	0xebabfee4
+	0x1f0e76e2	0xa07922a8	0x3a630243	0x41b8b460
+	0x11f8e1be	0x97ab45cf	0xd952588f	0x70461a90
+	0xdf62afd8	0x169cd499	0xc9a38028	0xe2d36ebf
+	0xa86477c5	0x1890d4fb	0xb78c189e	0x6002b07d
+	0x346599a1	0x998b8687	0xa073f3ff	0x561c2a62
+	0xc4904bcd	0x59a5194c	0x6b2d285d	0x3c7208dd
+	0x1a2e9b5e	0x7a7732a8	0x2c803c45	0xb307e8fe
+	0x9a402093	0x521740de	0xb25a372e	0x1abeec65
+	0xd9f84a17	0xed465fd4	0xfcc2e034	0xdc9bc727
+	0x9607ab7b	0xe0bd62d8	0x8630873a	0x361b3b75
+	0x603255fa	0xd815876b	0x32d0e705	0x5f99a520
+	0xf15a63b3	0x83f3009f	0x7ad4b916	0x1ba9093c
+	0x824dc86d	0xcd792af9	0x8d1e623d	0xad4877c1
+	0x2c09f508	0xab062540	0x242c5f5e	0xb46796bd
+	0x0bbc1a5d	0x02be8545	0x4ad68f23	0x370b4b1b
+	0xc16c7ebf	0x8b65ef74	0x11b64ded	0xc00f5586
+	0x41d6033a	0x0f79c8e9	0x356094c0	0xff3ec289
+	0x11a0d26f	0x347ebbef	0x23f2b11a	0xb6b15aca
+	0xe6856320	0xacecde47	0x513fbdea	0x7d7ac026
+	0xb72b0011	0x7d8cac25	0x222704f3	0xabc6b166
+	0x60995d26	0x95ccf438	0xce21d44f	0x27e15e98
+	0x9e229da5	0x929009b0	0xe79afdb0	0xf91bcab4
+	0xe5894312	0xe98d7607	0xb2bd2408	0x5abc5003
+	0x532b2c0a	0xb41dbdf7	0x248d6b00	0x7b811187
+	0xff7afcb3	0x818c2c38	0xacc7a704	0xaa14713a
+	0xeed076d3	0xcca8d4aa	0xd90177c0	0x9fcc01ae
+	0x8edd4189	0x1c896cfe	0xc4856a25	0xbeeb2217
+	0x52249b24	0xad45ff42	0xb43ae3a7	0x4bf0df57
+	0x91e369cf	0xcfafc488	0x6c218f44	0x0aab7b09
+	0x5f9c2410	0x87cdac03	0x986e83cd	0x56a7bba7
+	0xc7d2270b	0x467b995a	0x4b398fc4	0x64f04f87
+	0x30334708	0x8d0c7e49	0x69c792c2	0x725eba77
+	0x6870df0c	0x84d8a30c	0x0c5c6ac2	0xd9bc43cb
+	0xc52ab350	0x64878641	0xef306551	0xcfe54739
+	0x1aa176e8	0x6f1a7e1a	0x965be809	0x21e345f9
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+	0x629ebf65	0x613d8e8e	0x712a0fd8	0xbc88b08b
+	0x81ea88b3	0x3ac5f023	0xb93c236e	0x93a3468c
+	0xd86745c6	0x6df47eb2	0x10e2e256	0x2da86820
+	0x1513101f	0x38128155	0x7fbc9673	0x5e8aca10
+	0xc79677d1	0x8006a420	0x56909452	0xde047cd6
+	0x33256da8	0x63637d54	0xdbb682c2	0x9b00c56d
+	0x9f62d072	0xb7be713a	0xb0e603d8	0x047e37e3
+	0xd51ffb7a	0xeec69890	0x1e72d673	0x6d7f5c0d
+	0xa80c0473	0x12b89507	0xd605abac	0xd4c6899d
+	0x9bb98856	0xa6269a33	0xe08135cc	0x8a69b777
+	0x077837e8	0xd13014ea	0x9ca638ad	0x908e6612
+	0x5bf969fd	0xfd9da209	0x3e72a1a3	0xc7cbec2b
+	0x66cf84a1	0xd67e67eb	0x1684ed54	0x22feca3c
+	0x9c0d00c2	0x6337c641	0x89f65117	0x7fa4c657
+	0xebbd3208	0x89322dfb	0x925f82c7	0xebeef669
+	0x8cf74ade	0x55847368	0x28fd1623	0x5c2e0709
+	0xceb12802	0xbc4de4d3	0xec44bd13	0x33574d46
+	0xe89ce0f8	0xc09d2036	0xf83ce68e	0x0da18b34
+	0x30bd2849	0x252235cd	0xae7b84e6	0xb894640f
+	0x5b84fc6c	0x23f8cca0	0xd5a506ad	0x5605e837
+	>;
diff --git a/arch/x86/dts/microcode/m0130679901.dtsi b/arch/x86/dts/microcode/m0130679901.dtsi
deleted file mode 100644
index 11aaaa025a..0000000000
--- a/arch/x86/dts/microcode/m0130679901.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x901>;
-intel,date-code = <0x4212014>;
-intel,processor-signature = <0x30679>;
-intel,checksum = <0x69c4e6f1>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x01090000	0x14202104	0x79060300
-	0xf1e6c469	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x01090000
-	0x00000000	0x00000000	0x18041420	0x01320000
-	0x01000000	0x79060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x3b6ec6fe	0xc0fda75e	0xb4ea6a9f	0x8fd6ed15
-	0xd537f374	0x669bf3bb	0xebedec72	0xb4cbc889
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0xf03f27bc	0x3ed2262b	0xe1f8f63d
-	0xc164c68f	0x92e5df39	0x46108645	0x99a9968f
-	0x1dfa58a4	0xd1ebfd99	0xca4dae70	0xe466a06a
-	0x49575333	0xe30f49f0	0x814e5961	0xfa4bb7bd
-	0x2e212282	0x31912456	0x7d722c47	0x9cda0657
-	0x111985e9	0xd28d3b0b	0xec52f0c2	0x956b5b95
-	0x0806f491	0xa8096786	0x1e4c1248	0x42ea1ecf
-	0xea09d662	0xa821f68e	0x4b84d60a	0xa6f61348
-	0xfc95c139	0xebcebc32	0xd68ffe3e	0xa9aefabe
-	0xf653aafc	0x2a9f10e4	0xdaf3d51d	0x5f25aaa5
-	0xdedacabe	0xf2e08b12	0x6fb9f444	0x31b13d4e
-	0x13074cd3	0x68905491	0x08ce3a00	0xb3e5a3dc
-	0x9554ca97	0x5955c3a4	0x2e9951fd	0x5d708c9f
-	0xf3abe824	0xcb9105a1	0x3f51122e	0xd2152f23
-	0x2873cd28	0x463c0ff3	0x7bb81500	0xaa360665
-	0xbe69bdf9	0xa32415d6	0x111af68c	0xd129eaf6
-	0xdd102779	0x098a2b08	0x90363b85	0xdb5d3420
-	0xd1d116e3	0x9e5dd54e	0xb4a93d32	0xb5ee99fe
-	0x409f0bca	0x40302319	0xe175ddaa	0xfd7c8d00
-	0x2c28edb9	0x698d27f4	0x2e7945f1	0xc0150485
-	0xf9c599fc	0x139824cb	0x1571f70e	0x222565e8
-	0x3377eb7a	0x70fdee6f	0xd409f0a6	0xc875d05f
-	0x70d6a86b	0x66201d61	0xf8fcb733	0x14279707
-	0xc204e0e4	0x124c89be	0x8b298d1d	0x79bfe168
-	0xdbf7fe94	0x0358af09	0x8291ef8a	0x3e74a2ea
-	0xb7780782	0x0194d445	0x0bab231d	0xd76f85b2
-	0xc7510861	0x4b9a5c80	0x6c9c8583	0x4e18d7db
-	0x7dfeaea8	0x59be4d17	0x8e96f5b7	0x51bcb2da
-	0x5f3afeed	0xd3f46ecd	0x10da04eb	0x29dd87db
-	0xb7df24c5	0xd58dc2dc	0xede0603f	0xadf00cf7
-	0x50090b9f	0xc9130c82	0x854fc603	0x13b8b4be
-	0x10e2e41f	0x5c1d2246	0x0ee11843	0x6d38356d
-	0xd3bd47ae	0xb419f115	0xb118cac7	0x9c61aa7d
-	0xca22cf8a	0xd41af2f1	0x0b5ebfab	0xc0889746
-	0x078c705f	0x9e5b2b7a	0xb886ff49	0x1ab413e4
-	0x085cebc5	0xe3a44ab5	0x8844df92	0x075a79cf
-	0xb8fdc33b	0x1766265c	0x9340a734	0x4af860c9
-	0xa933586e	0x3e8a9a5c	0xf6419a1b	0xa70a1556
-	0xf930240e	0xe294fb1f	0x9bba35c5	0x4051819b
-	0x6799015f	0x7eb725ad	0x3953fe03	0xb8760679
-	0x54c7978c	0x3dfd36c2	0x631212bb	0xdeaca312
-	0x56d994dc	0x3a1696d1	0x214451fd	0x6dc505f7
-	0x7bbf210f	0xa266b569	0x8fb5eb6f	0xa6b76bf8
-	0xc9e782a1	0x8456765d	0x0a9eb223	0xa67e533f
-	0x211016f4	0xd8783c3e	0xc35574b8	0xd97e9b52
-	0x28ad2911	0xbffc5dad	0xd807d783	0x3050f3d1
-	0xcc33efa8	0xb9cf97c2	0xee5dfc8c	0x2adad5bb
-	0x4011c50b	0xa16f5d93	0x5e2ac188	0x521c977f
-	0x6af1b858	0xcd7e4b4c	0xfc988f66	0xc0e4cee9
-	0x82ac99ea	0x54353832	0x2308e02f	0xd084d198
-	0x03574ad5	0xbe4b698f	0xe1d7d294	0xd772d08d
-	0xb7a4fb2a	0xf7c93bb8	0x42fb2f4b	0x98cb1a11
-	0xf564f28e	0xd6ace35f	0xc43f6639	0x85be741d
-	0x079b8c1f	0xb5b45522	0xfedab918	0xf7fa7494
-	0x32204c16	0x1c8d5434	0xc39e58e4	0x99c7a2c4
-	0x3ccfbc3a	0x3f5ba9ef	0xf919921b	0xcffbeb79
-	0xd2927d86	0x5a50486d	0x62bdb218	0x22731dcd
-	0xbad1db2c	0x2f4af4a5	0x8f7eded6	0xeca3dcca
-	0x0bb5ecf7	0x05e6f3c6	0xa38cddff	0xc7cae177
-	0x1d115485	0x711ea542	0x33729cf9	0x59000680
-	0xcaf26070	0xd2647235	0x4ce354fc	0x76d9bdbe
-	0x53e39ec2	0x2d8acfb3	0x193c03b9	0xb3cef3ba
-	0x1da26bd5	0x8dfeeaa5	0xc199d90d	0xcfc8ee2d
-	0x4cb1bd52	0x521d197c	0x008bf34b	0xb6ff25ca
-	0xf4922b7c	0xa91893a8	0xbd3d7874	0x32865e72
-	0xca72c49d	0x02733201	0x6156051d	0x47464b81
-	0x353a3c14	0xa87475c8	0x9681a015	0x4b58832d
-	0xea65c6a2	0xfefef1fb	0xd5fa7dbf	0x13aeee80
-	0x2915b47b	0xe4a54fca	0x31615326	0xbad80f83
-	0x21eedfcc	0x2a2787da	0x6eaa2c9c	0x9de76356
-	0x8a34d823	0x2e7641b8	0xef16714d	0x8267bad4
-	0xacdfff45	0x09a93862	0xf63863de	0x7eec7d8b
-	0x70b4cf72	0xc7a8118c	0x4ed89774	0xc12a5e0d
-	0xe77cc023	0xcdee8fd8	0x20ffe6d9	0x88bcfaa0
-	0xd945e4fb	0xf496fccc	0xe7587e99	0x42252ec4
-	0xcc47d738	0xcc549ca3	0xd5059657	0xfbf502a5
-	0x2788945d	0x4f8ca4d6	0x41b7c069	0x618ebdf6
-	0x0354452c	0xf7249d75	0xe048dd38	0x4ca484b3
-	0x0347342c	0x23608b20	0x8a76cb28	0xd445886d
-	0xfe0e1e6a	0x46678478	0x230c0ef0	0x3add3053
-	0xa6a158c1	0x22c589d3	0x3b728538	0x5f78bfe8
-	0xab0bb3ab	0xb39e20b7	0xbb913a69	0xdf8bb73c
-	0xc2d5bb32	0xbd3e928c	0x30374965	0x9accaf18
-	0x60bb410e	0xa7786a6d	0xd368444d	0xc5eda57d
-	0x7a835abd	0x9f5f74e9	0x33b14a30	0xc0129833
-	0xc5d2e117	0x5f884f0f	0xae6fd2f7	0x3ef71ba2
-	0x0f0b944c	0x1a8dd932	0x2448f0ed	0xfb8ca949
-	0x9d08756f	0x7914384d	0xdd70f795	0x8cf8daff
-	0x6755785b	0xf4e6a191	0x8c5a9a2e	0xfdc19939
-	0x66f39dc0	0x3da9fcc2	0x2c22797b	0x63f892d3
-	0xdcb75a66	0xa043c021	0xcb0f9292	0x887eb1a2
-	0x9d588452	0x9fdc185f	0xf481d465	0xbfef53b9
-	0x38da9baa	0x9d35c4f4	0xa652c843	0xf80f0007
-	0xb482a32c	0x7ae4df5b	0x74ad41c2	0x15d849b3
-	0xc4235054	0x36d44d98	0xc06ad604	0xdc83d81f
-	0xd4b87511	0xab79b430	0x832a7ce1	0xafe26f16
-	0x9f7d26db	0xd00816cd	0xec6e7b8b	0x0392bd20
-	0xfe4b6e2f	0x87795026	0xf9e4eef8	0x06cd2ec8
-	0x91670e6a	0x17aad6af	0x399050d1	0x043d05f8
-	0x5dd8e105	0xa2938113	0x2c47ea5e	0x64a062f8
-	0x14dd01cf	0x6773f479	0xf2b4a773	0xeefe3b89
-	0x8cf35404	0x0f02b236	0x430023ff	0x04ecae31
-	0x6949cdfb	0x65b63ba6	0x86c5a7c6	0xd53cc1b5
-	0xdc1ee770	0x30ebc654	0x67a95215	0x2e4508a9
-	0x9df37690	0x33baf9e5	0x9a58d5c0	0xe99baa0c
-	0x4b7446eb	0xfc7c8340	0xfa5ee60a	0xd1d873b4
-	0x302f882f	0xcff8ac83	0x56d809d2	0xcab281e6
-	0xadca5551	0x50691975	0x7766b753	0xdb7adecd
-	0x131c83af	0x1b09ee46	0x87fdd3ef	0xfe3037c2
-	0xcd2b5362	0x5f21384b	0xacd78f4e	0x145a4793
-	0x131a6a20	0x0fc1adf5	0x3707f20b	0x5d37ba20
-	0x6c8448e6	0x76f721a4	0x348b0456	0x608453ed
-	0xb1185c8a	0x18bbdaa1	0x7c1c6e05	0x46fa7cdf
-	0x390cf9b7	0xe9c825bf	0xf77554c5	0x7dd5a47c
-	0x49cfca16	0x5fd7e6dd	0xf707ac36	0xdb6f0142
-	0xaabda9b0	0xe7ac02e7	0x0a1eb844	0x225686b2
-	0x7852c1cf	0x3912115d	0x89d65081	0xc3f4faee
-	0xfedeba97	0x073395d9	0x33d20ce3	0x56c6c126
-	0x378f822e	0xf575b487	0x043da151	0x1ccae8c2
-	0x5fa2279b	0x0608f618	0x4c90662b	0x30591d0c
-	0xcf217166	0xacdbf6fe	0x1a653b17	0x6fa76090
-	0xc804480e	0x44c5b06b	0x1ebb8a6d	0x2f6f6f08
-	0x6bbeb75c	0x21c5c48d	0xd4c4cc2d	0xfdeab68f
-	0x25cd39e3	0x62970aa2	0x48aa915f	0xca38c833
-	0x9cfd1d10	0x81dbc61d	0x51702e45	0x8f80e492
-	0x07e89651	0x920e9f7d	0xdfa9f973	0x8cbfa187
-	0xbd3e7a14	0xee191486	0xb0077d2e	0x7345adcf
-	0xce36b2ea	0xc73aec7d	0x9278ac37	0xe07c6d96
-	0xf90f78a5	0x38f5584c	0x4941da80	0x67ff3048
-	0x3c263914	0x49656179	0x22f066a5	0x1f5a5e3e
-	0xce9ce83f	0x8e7446a2	0x85473d62	0xd7622673
-	0x3941bc22	0xf879d494	0x0936a517	0x2bba925e
-	0x516761b3	0xe238a8e3	0x11a0c8bf	0xd53cb861
-	0x60c0f0d5	0x63f7f157	0xb23dd4f9	0x5a4fd86c
-	0x3851d435	0x483b98c7	0x71c55b1d	0x1931d219
-	0x7bd54621	0x108bb4af	0xa72c8b97	0x51d985e2
-	0x598a521e	0x7efcf984	0x69b02671	0x5746157d
-	0x60cfc339	0x629567fe	0x2236a93a	0x520d0094
-	0x61811f40	0x856aeba6	0x4fc0a2b3	0xedcc9fb2
-	0x8fce6123	0x2ba53b1b	0x6fc610d4	0xabb564f4
-	0x957158aa	0x1d2b7989	0xaca5dedc	0x684a7086
-	0x1610e1ef	0x2abdf9b0	0xd9e9d205	0x0119ab86
-	0x6da64982	0x71f274b0	0xf425e61b	0x029dc92f
-	0xb13ff88f	0x064ecf92	0x4070c36d	0x58bd6ebd
-	0x629bcf8a	0x9091566a	0xc947a42e	0xd0475c87
-	0xe7773220	0x7b61f2fc	0xae0c08e3	0x44582521
-	0x557dfbaa	0x92fba0ef	0x529900aa	0x90fef908
-	0x570b0495	0x704125df	0xd8f9448e	0x9a7cf1f3
-	0xd83a747b	0xe27e3d56	0x4da6aaa3	0x55439398
-	0xce0d1c02	0xdebd6473	0x580f141b	0xcd5a5e57
-	0x1c64cc23	0x53f8f9c7	0xcfb5b464	0xa4939b05
-	0xc0bb3066	0x37923d76	0xe5e9b428	0x6f4f2894
-	0xe5144757	0xa9cfdc46	0xe3448b78	0x7e0bac3a
-	0x38066245	0x0d7c86fa	0xb7fd09a6	0x075426bf
-	0x3de7c82a	0x1f8d1b36	0x34144ca2	0x6c03ad9d
-	0x34305ef0	0x0a5269ce	0x82a9eeed	0x3be63f82
-	0x2001cea7	0xbba641a8	0xa4dad9e4	0x92e0fb69
-	0xa166dfad	0xd1ae10ab	0x0372e102	0x88469aeb
-	0xaa11bae9	0xf1006dc9	0xa8648217	0xe171b6e8
-	0x590ba849	0xa593cf1f	0x4cf079d4	0xe451e193
-	0x4355a93f	0x54dfcade	0x1a918a74	0x88eff191
-	0xd5a2bf54	0xb9962550	0x58d478ab	0xc78828a9
-	0xe2cff385	0x9ff810e7	0x9643953f	0x84764dee
-	0xe4950d03	0xdf17e0e5	0x4da892d6	0x48145872
-	0xb7453254	0x41240a2a	0x7ddf94bc	0x898771f1
-	0x61a423be	0xcfb46db4	0x7db27a89	0x2feeaa82
-	0x24d86326	0x043f5b1c	0x8cc6bd73	0x934b7b3e
-	0xac4a1262	0xebc494bd	0x53921696	0x115c4d9a
-	0x1d73de18	0x6417f141	0x9fdce4cd	0x8f72ccdd
-	0x3bb26030	0xdaf43da3	0x1e26758b	0xad1234be
-	0xe5bdf477	0xd2dd9e46	0x1270838f	0x557f3bd2
-	0xaa5a28c1	0x61e0d535	0xdc5aa028	0x9af22a6d
-	0x9b669fbb	0x979b5586	0xabf8264f	0xbcf91b17
-	0xda92e3cf	0xaaa87ae0	0x52336f6d	0x5beef95f
-	0x7c310125	0x8858f708	0x3c6e6d73	0x6720d3c6
-	0xed51b365	0xa9e50de2	0x865a7fc1	0x756b5758
-	0xbe13f4ca	0xf2eb039e	0x187d1641	0xc6e37977
-	0xbc3a2d64	0x6523583c	0x70db0cf9	0xebdba06e
-	0x632e8e5a	0x7b44144b	0x338bf7e2	0xf43dd8e4
-	0x2d91d815	0x9aff02dc	0x700ebe20	0xe9b6ea5f
-	0x776cdc38	0x43324788	0x53458290	0x2e22910d
-	0xed0fdf3b	0x279fc3ca	0x5a01f65c	0xc4ad1598
-	0x7a1fa09f	0xd12f97bf	0x34d99bad	0xfcecf69c
-	0x2b5567af	0x57a93cb3	0xfcf93005	0x3a403789
-	0xecaad383	0xc63fe190	0x5b8de563	0xbd9b876d
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-	0x72b4d6c9	0x54df0f5b	0xbcb2bb34	0x20364bf2
-	0x9fc24cdf	0x83452f28	0x734248b7	0xc698bf34
-	0xee328cdc	0x8e4bff33	0xa1addacd	0x07af68c8
-	0xc34b5d25	0x8e611a0d	0xcbb8ff85	0x077c6d43
-	0x95feb2a3	0xb435fffc	0xef5eca7a	0x0ff6045a
-	0x449647ba	0x75795c99	0x9c514436	0xabbe74d9
-	0xd180f18d	0xdcdeee76	0xa9550f7b	0xb4c8e109
-	0x80b21662	0x8a407a0c	0xa6245b13	0xa16f44ac
-	0xb3db67d3	0x0b335cfe	0xd878e875	0x81d6df28
-	0x44871141	0x6a6dada5	0x7f97fcd0	0x7ee87f79
-	0xddc5bcfa	0xfc2763db	0xb11a9212	0x94ba7acc
-	0x49428749	0xd219071f	0xd91bc4c2	0x4ad5c326
-	0x54ea2297	0xdb16bca5	0x33327f3f	0xc487b8c7
-	0x54ca8d94	0x4c6f5655	0xf51c3911	0x37931433
-	0xf6506856	0x6b5a93f8	0x388950b9	0xdf5263b5
-	0xd4cf56ea	0x8da347e2	0xf20a9a39	0x1a6b8e4c
-	0x2ce3df55	0x38269e78	0xdc7a9762	0x9e73a3dc
-	0x57de6fa7	0x9c2573f5	0x3491629e	0x009452fe
-	0x8a34ddd1	0x701df9ab	0x4035380c	0x6f25e16d
-	0x0ca914de	0xf9277a06	0xca1f1fe3	0x95aec5b6
-	0x7a613e97	0x52e77607	0xd7229ff0	0x5f301016
-	0xd4e142c1	0x29a939cb	0xe96dd1ca	0xc953aec0
-	0xbf02c31e	0x02135076	0x4f931dcb	0x4b280cd3
-	0xe0cda493	0x70831c04	0x8192143c	0xc9f94a3b
-	0x13eda1d1	0xc62c39ad	0x754a5411	0xe43ce416
-	0x95ac1b10	0x871261dd	0x79f33a8a	0x77383224
-	0x98b2480f	0x2df139d4	0xd753e53b	0xbad87b53
-	0x977cc17f	0xacc4bb71	0xbde6b5f2	0x206562ae
-	0xe0319086	0xcf903501	0x56ed1506	0x64f4556c
-	0xb90bbe0f	0x2def02e5	0x9b625a9b	0x96086cce
-	0x39d1d0ab	0x8c85c5d6	0xa8199040	0x23c770e2
-	0xf5303bd0	0x51a83607	0x5afa1989	0x8a81b4ff
-	0x1b24e6a4	0x4cb58014	0xbbee7d31	0x758271fd
-	0x259bc3f5	0xb3f9c6eb	0xbd8c4f86	0x66c27a35
-	0xa41c2904	0xc9848ce3	0x9ba21676	0x18f65508
-	0xe5637556	0x031e21c0	0xc09e3c77	0x5f10856f
-	0x9b3ea697	0xd8afe20b	0x447f5be1	0x5c4b1668
-	0x71f44cc1	0x8637d0c6	0xbd182081	0x1e4221b4
-	0xd312a403	0xf49d2c96	0x686ff9e1	0xa3f9b746
-	0x3caeae90	0xf2bfb131	0x5823eb37	0xcd4edc6d
-	0x3a7f65d8	0xbb4be9d3	0xd7939b2e	0x71d03a37
-	0xa30ff63a	0xde7ccb57	0x8ea031ba	0xbcb3994d
-	0x8018d6fb	0x1c7a3610	0xac900573	0x9ad05089
-	0xe2d17d5e	0x7816b9a7	0xffcca5c1	0x9faa9a0c
-	0xadbe99e6	0x06de7ee1	0xe4ac8981	0x29ef423c
-	0x32219ad2	0x806642b8	0x412ab076	0xfe4c5196
-	0x82c2507c	0xd58c7b7c	0xfe9edc9a	0x89e4c6e9
-	0x4f122269	0xf0aeb2f1	0x77f4fbc0	0xe6692464
-	0x6e64c198	0xaf79a455	0x01e2ed98	0x897ec1b0
-	0xf7a0dd35	0x92baec5e	0x93f17b7e	0xfbf82b90
-	0x168d32c5	0x741b61c0	0xb0f5b9b5	0x0557fb71
-	0xca937e89	0xad652a2b	0x9a2121c8	0x34d189ca
-	0x037dd1a3	0x3e650192	0x4defbaa7	0x06763750
-	0x48d4d1b4	0xda2af400	0x7df71d63	0x3e0b4c46
-	0x28c645bc	0x29b15428	0x34e10558	0x1166cdd6
-	0xc259a364	0xdc7e0f21	0xb02cee35	0x3055f39b
-	0xb77a50d2	0x2c143c84	0x7903e30c	0x018e20a8
-	0xf95b4a26	0x38c84311	0x1f0c3098	0x535a95e7
-	0x730214dd	0xb0f90f53	0x625fc5d1	0x2c1f2d76
-	0x7c9b5351	0x5cc285f4	0x0f63b5f4	0x90d59d57
-	0x140213fc	0xd21a74b7	0xf85fd83b	0xd9f21e94
-	0xbbefcd30	0x5091f90f	0x8d5c47fc	0x9455364a
-	0xef89f274	0x901af041	0x782cd03a	0x086f1f81
-	0xe09eb4db	0xf7a8146c	0x41898271	0xe8be480c
-	0xdfbac329	0x5fb899cd	0xfdca25e8	0xe994b3d8
-	0x2299ede3	0xc0341512	0x0128eb87	0xd5cff619
-	0x779bba38	0x1e986657	0xc22ac15c	0x919af309
-	0xd3cd1df4	0xb4b22d9a	0x210c0617	0x5723f9e0
-	0xb7b79328	0x613e738d	0x39057942	0x48d48958
-	0xf9d80cc0	0x16f69a5c	0x6d517734	0x012f07fa
-	0x7a8329e1	0x586b22c3	0xdd0d96b9	0x0c56d5f9
-	0x60410aa3	0xd1975446	0xd2c142fa	0xb13ba75b
-	0x0b046c21	0x03afb4e0	0x346f5dce	0xd108fa96
-	0xd1ca963c	0x73f5838a	0x4b4f734f	0xa1d430a7
-	0xd0cda381	0x64fecfee	0xc5048480	0xd3bfb251
-	0x088982f9	0x2383aaee	0x9b9c8f48	0x623f2132
-	0x0f5ae663	0x3c32959a	0xa1fd9ecc	0xf62d0e4c
-	0xe690d930	0x6be7a286	0x825d0066	0xe51094ca
-	0xc99affb8	0x832222ea	0xe7296513	0x2c040c86
-	0x35f62e4f	0x6f46ba84	0x25cdb0a3	0xe8b6ec22
-	0x5b6cf8d0	0xcfd85f8a	0xf0181633	0x5362c0b7
-	0x58955c60	0xc5a36973	0x874d04eb	0xa42a42df
-	0x4bd5d994	0xee6114f3	0x671ccecb	0xf0ae2422
-	0x70c98042	0xf9ed2a1a	0x6b60f0c9	0x04b13374
-	0x96fba002	0x8b481645	0x315198a2	0x65c80b9a
-	0x31475dd9	0xe95c5c3a	0xe3c22d43	0x12659565
-	0xabec6f96	0x9446e315	0xa6552f83	0x295e2596
-	0x8b6a2d9f	0x71efb10e	0x2d309912	0xe3dd2879
-	0xabd39f50	0xcfa94a90	0x61d282b7	0x062b246f
-	0x617b7162	0x3628fffd	0x93c8c8a5	0xaa44c72a
-	0x11b78bff	0x8259874a	0x186bbcfd	0x37bf7395
-	0x6f8582a7	0x65fdd21b	0x53106cb5	0xbfbe1e4a
-	0x1ed99eac	0x670b3763	0x245db7b2	0x7584d9be
-	0xc3472009	0x572bddab	0x17e7406c	0x79e0ea4e
-	0x74779fd3	0x92d0c51a	0x1808d006	0x46c1e76b
-	0x40e48bf4	0x61e17325	0x1d437ab2	0xacf51c38
-	0xc19eab2c	0x02957308	0x0bcc40bb	0xf603815f
-	0x9c666571	0x6a7d539f	0x57f3941b	0x7af81d5c
-	0xad1427b0	0xc188d623	0xac010003	0x1ff4cdf6
-	0xfa504446	0x6425ba6c	0x27ff69fa	0x26da5613
-	0xb6fc0a69	0x1155853e	0xbab81c6e	0x3dc17909
-	0x07b209d9	0x8b269554	0x73fc8781	0xfc1c2c82
-	0x572df087	0xb71bb5e5	0x55f9d202	0x6f525daf
-	0x117755f9	0x52cce1bb	0xa789ed0e	0x1313ca47
-	0xe8bdd878	0xc37e8dcb	0x53b971fc	0x43540a80
-	0x3d2384a7	0x25ac992d	0x7aef31c8	0xb1294afd
-	0xb0a34878	0x96e9ca1d	0x82a19bcd	0x08cd2bdf
-	0xd2681e35	0x2d32fa5f	0xc7c0c8b2	0xeecd089d
-	0x97404355	0x0b34539d	0x37ce4df3	0x599352dc
-	0x06734f29	0xf47ab5d8	0xb15ea9a4	0xfd92ed2f
-	0x9510bdbd	0xb740d34b	0xbac3e94a	0x52efbc03
-	0x40bd7acb	0x1bf83a4f	0x3d76c698	0x7e691383
-	0xec85e4ae	0x55e9a446	0x1fc3ab3b	0x6aea12fe
-	0x8fab4a84	0x69cd7328	0x935a7236	0xc3f59437
-	0xb73a7d8b	0xba0f54e0	0xe8e7aafc	0x6f82ade6
-	0xed6ccaf0	0xdfddc46c	0x0763fc3e	0x778e488f
-	0x0bcc4dce	0x8f919858	0xa7bc7d1a	0xd4954eea
-	0x517b5458	0x6c3f5835	0xd960f76d	0xf5be65a7
-	0x133666d9	0x4431f94f	0xccedf47d	0x6eb21ff8
-	0xb858dfef	0x15beefef	0x9a1b6b6a	0x64890eda
-	0x2a381329	0x660302bb	0xc65c001c	0x049a4be4
-	0xfca1b112	0xb081a099	0x3a2217f8	0xeea9a2ef
-	0x7719129c	0x7c915047	0xb3fe3e16	0xf1c31548
-	0xfa84a76b	0xd7af5b51	0x0de24c14	0x89a7263d
-	0x5a9dbffe	0x7ea90ae3	0xc21a2a1d	0x65ef3a3e
-	0x90fd1fa0	0x69aa0d9b	0xb44a5778	0x5ded34b3
-	0xa0d78617	0x91817661	0xf9541869	0xa0960273
-	0x024d891a	0xbc9f6d7a	0x630bac04	0xd186ffe5
-	0x0d60d640	0xc05e4701	0xba72d775	0xacec7c0c
-	0x1680e76d	0x6b153d69	0xbcbd60c1	0x3e1ed6c6
-	0x9705975b	0xaa3cc082	0xbdd723d0	0x7c0bbdd9
-	0x2bcf8414	0x787b2dea	0xaf923561	0xe4ad94a2
-	0xa85f83a1	0x1de0ddcf	0xd96f918b	0x617b1461
-	0xb1d3e386	0xe8d80b5d	0x40dad53e	0xcd8fb285
-	0x46fb4bae	0x2845c456	0x8b261251	0xf4923055
-	0x99d0db1e	0x0d7cc781	0x9bb20af6	0x7116d81c
-	0xd7f54821	0xba4eb2d0	0xaef6b275	0x3ca796cf
-	0x8807360c	0xd887484b	0x7066ec38	0xf7262152
-	0x5ede9cc5	0x6b8eb00c	0x5564b7af	0x4726dfd1
-	0x9421fe95	0xcc0ff9e5	0x10ca7e89	0xb76760e6
-	0x3da3a50a	0xf9cd3f82	0x1eb01d3c	0x13ae6371
-	0x129747e6	0xab223504	0x9978c7e9	0x1f7ce259
-	0xb17fb162	0xd1ac0e80	0xe04bfd17	0x197d9eac
-	0x59586a32	0x7436e8ef	0xc28b1ec5	0x83af0dc7
-	0x8382692e	0x17f04148	0x31ee5ad3	0xfe89b973
-	0x0148467a	0x1a6a16ef	0xb6400bcd	0x53ae7036
-	0x6b258693	0xb6edbeca	0x2ff0b686	0xe6f0c346
-	0x0e0ff99c	0x8d369a6e	0x7d10411d	0x2ebccabc
-	0xa67435d3	0xf9901563	0x363f164f	0xf01a1b15
-	0x93b6a10f	0x81f0c068	0x89b8423d	0x60eb711a
-	0x4e45bf98	0x24845e1e	0xda91d7f7	0x561e7ab1
-	0x51a183de	0x73bf29a6	0xcdb20f84	0x46d5ab3d
-	0xce01efbc	0x8d09be04	0xbf4aee2e	0xadf03a7b
-	0xbc454c61	0x83647148	0xec9e834a	0x11527826
-	0x2c7eb009	0xc6d7e3f4	0xbe8befd2	0xd3cc42a8
-	0x0442b41e	0x89643506	0xfd1dc572	0x74b340bc
-	0x686f6f6c	0x48b92189	0xe8f88be6	0xfc591dbf
-	0x8b453678	0xea1fd8cc	0x659d57d9	0xb501f90c
-	0xa6d6b031	0x182d8378	0xd6a8d690	0x6419c2b6
-	0x523d3089	0xc23c971c	0x43994015	0xa4b23066
-	0x831e6ca5	0x03c18610	0xd6d1f4b5	0x28978a3d
-	0xdc620eba	0xc1f86faa	0xf6c4d906	0xf06f85f3
-	0x232fa1bf	0xcf80cc2a	0x6599a5b2	0xc2d4cdad
-	0x0287eb92	0x5cdc4dd6	0x34a9b6d4	0x6d4b1324
-	0x6d21a837	0x00026037	0x80a225a8	0xad75b226
-	0x414a3741	0xb74d0962	0x363b24b5	0xb5044295
-	0x0a01c1a1	0x90a110c8	0x53bdeee5	0xad31aa53
-	0xfb85cc5f	0xdf80b0f3	0x7ad3cb0f	0xb5c68bd6
-	0x89185ff8	0x41544629	0xad5adfe7	0x39061752
-	0x2e9c106c	0xbf52a0df	0x9d2cef79	0x99eba49d
-	0x4459b32c	0xdc98fd7b	0xd81f2f74	0x8aa59f53
-	0x1817857f	0x5f79e3bf	0xc4b7c810	0x9e3a9ddc
-	0x724af115	0x121239e3	0x3c33c849	0xd8abb44d
-	0x600d67b7	0xeaa06b4c	0x20fe7ba6	0x502c684b
-	0xf212d37d	0x413d883a	0x5abc83ec	0x3112bb6e
-	0x27e1b3e0	0xf6dc8508	0xfe602c4f	0xa5b34bce
-	0x4d03d689	0xdacb23c2	0xa00fb513	0x78606ea8
-	0x8fd43ecf	0x90072d2a	0xfcc7b1b9	0x7ffec951
-	0x684bbc25	0xc21a0374	0x8f06a016	0x0e28dfea
-	0x40da3a00	0x8c73a059	0xc0d565ef	0x13bb6c81
-	0x6e27c2ec	0x2f4c9a43	0xae1b4513	0x9738b38a
-	0x5557c3e1	0xa292c6ab	0xd0f78cea	0xb96402f7
-	0x6c281a04	0x948787f9	0xe59f0714	0x6f130446
-	0x4b12e263	0xcae5e073	0x00f0e279	0x9b03c647
-	0x2a141b72	0x19d1e112	0x97b3b6df	0x3c2b6c82
-	0x5b119136	0x57e2084c	0xe954bc0d	0xcdfbfa78
-	0xadc6b571	0x010b9122	0x236676d6	0x2458c822
-	0xcbb8384a	0x662cfd01	0x096c50d2	0x4959676b
-	0xf8b59f31	0xad912a4d	0x2e87fa6e	0x30182092
-	0xc0bf2c01	0x02b4bfa7	0xdd208dac	0x4c174da2
-	>;
diff --git a/arch/x86/dts/microcode/m0130679907.dtsi b/arch/x86/dts/microcode/m0130679907.dtsi
new file mode 100644
index 0000000000..30e2f9e527
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130679907.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x907>;
+intel,date-code = <0x11142015>;
+intel,processor-signature = <0x30679>;
+intel,checksum = <0x1bb67b21>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07090000	0x15201411	0x79060300
+	0x217bb61b	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07090000
+	0x00000000	0x00000000	0x13111520	0x01320000
+	0x01000000	0x79060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9703f29f	0x1c68d65c	0x1f15f858	0x114237f4
+	0xfef8d172	0x363b5a9d	0x4c3d9e71	0x13ff68a0
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x46e87267	0x7c9db265	0x4ac824e5
+	0x94ed53c5	0x4b1bbf81	0x241a4da8	0xc3c5d866
+	0x186d6eed	0xba1e5092	0x3d19677c	0x82b56f7d
+	0x95d4d506	0xdccbbfb2	0xdc6be978	0x416dbe64
+	0xe591ce22	0x02987636	0x44858276	0xfbe3729a
+	0xee42767f	0xb415639f	0xbc959b72	0xa6919bec
+	0xb9e2d0c5	0x2fb1e39c	0x1ebae20a	0x9a3ce21a
+	0xebf72206	0x4020d73c	0x92674cff	0xbc607b8d
+	0x488d8dc0	0xd1d6f435	0x39e3ee1c	0x1ed65078
+	0x967d7a88	0xaa1b9f3b	0x38248bfe	0xb8a0aeb2
+	0x3b8e34fb	0x86dd48e5	0x887d7432	0x3a3a3faf
+	0xec556202	0x50ebe457	0x7676b9bf	0xe84604b0
+	0xcb26a17e	0x52c94055	0x6b39d618	0xa82d63dc
+	0xf583cafd	0x32107d4e	0x71d5aee8	0xad5956f2
+	0xad58e817	0xb6da62b3	0x66d63e32	0x00a13bc7
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+	0xd5839e6e	0x00635ed9	0xc51b8d91	0x34e60826
+	0x08082536	0x3550eed6	0xc78b127e	0x2f428ec3
+	0xaf95830e	0xb0c8fb6c	0xc0b5e989	0xb45d0020
+	0xce6466e0	0x8e244ba2	0x17ef4563	0x2c74b037
+	0x8d15449e	0xa96ad89d	0x0672ebbc	0xf5a037f4
+	0x633b2cd2	0x82d1cb6a	0xeae7ab21	0xfe156394
+	0xb223326d	0x6bf37192	0x349934ac	0x747e4995
+	0xfff3f992	0xe916d599	0x95917b72	0xd3e810ad
+	0x704231a5	0x041ed2f0	0x32cca85f	0x2ceb1663
+	0x80d3e7c7	0x901d33a6	0x18a99b15	0x21b50c44
+	0x295e5a16	0xceab5147	0x503b6e34	0x732a4fdf
+	0xb6b38684	0xa1317fff	0xb76492ef	0x88e7eda4
+	0x5ccde55d	0x7448f240	0x12d3436b	0x6a152377
+	0xff0b0448	0x8b124b95	0x55321a93	0xed4229ef
+	0x7ea05a46	0x992eb553	0x5f2d7278	0x90dd258f
+	0x6ecd1946	0xab971c70	0x3d341faf	0x49855465
+	0x1973c8cf	0xb5976088	0x6640e00e	0x155dd9f3
+	0x674285a8	0x720515e1	0x5fdffc94	0x0d3a3347
+	0x1dbfe5ff	0x7079f37e	0x8c470652	0x46d6c1e3
+	0x1402e1b4	0x05217695	0x67e45039	0x683ba960
+	0x97cadd4e	0x59664501	0x4726c2a6	0x7601358b
+	0xec77b4b9	0x66a912a0	0x8f157d86	0xa0e221ba
+	0x3aa4bd23	0x547e9323	0xaa94772a	0x1ba6ac0c
+	0xbed2aa6f	0x8a945e94	0xeea5c775	0xf2c66a89
+	0x89ebde2f	0xd7b4e71c	0x6a1c8bb3	0xb9392201
+	0xc7a2191f	0xf180c19a	0xc3446d78	0x7f5f61c8
+	0xc6a251da	0xa27c507f	0x329133a1	0x0c951593
+	0x344ca56a	0x329dea98	0x73112997	0x32bc47a4
+	0xbeb18227	0xd3347aaf	0x1c481ab4	0x62606e69
+	0xe18da26b	0x8243c025	0xfe05b066	0xc1b0c590
+	0xd8c107ba	0x235b8c6a	0xac4fe894	0xa012810b
+	0x5470e6de	0x6f1217ae	0xcb099ad1	0x2b03655e
+	0x91f0b417	0xc21a1af4	0xb4a8c50e	0xa5988ed2
+	0x7f03fa1e	0xa0658a65	0x5532c4b3	0x1fdcfcec
+	0x17f41c26	0xd6b29efb	0x3411f331	0x1b774029
+	0x2ee2d094	0x9f5edaab	0xc644a9f3	0xdc4cf7b1
+	0xb6304748	0xb064cfca	0x89e4dbee	0xb1563a5e
+	0xd370bca8	0xe6cb17d8	0xbfcacc87	0x76940250
+	0xf2456a18	0x3c1873e4	0x0a3d7d0e	0xeb145eb9
+	0xe88a48fb	0x9413f290	0x626e4e00	0xb234a13b
+	0xcbf49379	0xcf600cee	0xc78891b8	0x799f8e80
+	0xdbf4e604	0x89860862	0x04fb77db	0x0fb1bf13
+	0x3b1aa906	0xadaf9a45	0x48526bf7	0x09d8ffb3
+	0xce751581	0x00e35b8d	0x0549e629	0x6d3cc316
+	0x3d8f300a	0xdcd790b5	0xde1ca316	0x737d5f31
+	0x171b2646	0x4798a85d	0xea36f650	0xcf889098
+	0xe4ec65b8	0x944637d3	0x019c8103	0x5fbdc21c
+	0xa61ebe77	0x74ea95a5	0x258eb8d1	0xf8c8c4d6
+	0x9a1edc66	0x9118b309	0x639ae9b5	0xd0c40735
+	0xc6ddec32	0x36d26a75	0x86018c99	0xe8bf66df
+	0xf345dba0	0x780670a3	0xe34e60fd	0x733ad4ba
+	0x2ef04d54	0xb1b9c41f	0x84cca1c2	0xaa09279b
+	0x34797d41	0xb93d4c70	0x919ce970	0xd0d6ec5e
+	0xdc70cc95	0xd89f4680	0x458cfd33	0xc257784b
+	0x29ec9364	0x8e717417	0x6d9732df	0xa3658440
+	0x8574b5c6	0xa58ebb8c	0x81bc4dea	0x1f396663
+	0x361dfd98	0x20b35a46	0x886a7e4c	0x69f0a1c5
+	0xd0b7de5f	0xbbc08761	0xa1cef991	0x084a8ea2
+	0x4df68c5b	0xb84b4b2e	0xd4bf1770	0x94b4f7c7
+	0x9906a752	0x878c7f1f	0x385b5a5e	0x99147c87
+	0x97c54a35	0xbacb57d4	0xf85f9733	0xb5d2c83f
+	0x4405f9f5	0x020260b5	0x5c0a8556	0xb623ad79
+	0x8d42a6a3	0x35ae5806	0x2c28a60d	0xa0200ee8
+	0xed9e0ece	0xb7e0442a	0x1ddf0e2b	0x26ceec5d
+	0xda397b2c	0xb073d9a2	0x9d856bbd	0x06e35ca8
+	0x6296193e	0x292dee18	0xf5a9bd7a	0xb62fe73f
+	0x95a8775f	0x1efc0fd0	0xf3338af4	0x06ccbe78
+	0xafb3f669	0xd9f7fe16	0x09beed63	0xa2f0bb3e
+	0x02f5c52f	0x24aee650	0xf715039b	0x3f566d89
+	0xd575429b	0x9d40207d	0xa89c7de9	0xde5157f0
+	0xd79025ae	0x4259c4b6	0x61e86217	0x6d2e3273
+	0x57b5c99d	0xa18edb02	0xf5f314be	0xfa58bf5f
+	0x581e95bb	0x04967c03	0x9187d903	0xdaf34bc3
+	0xa18e49f0	0xb7973963	0x2984967f	0x7332f94f
+	0x57e5a8b5	0xe6e0a6f8	0xbc08c39f	0xc9e73ad8
+	0x0ea113d8	0xa9cfdb06	0xfda1ebbb	0x1a30e9f9
+	0x69a9029a	0x44b43320	0x04182d93	0x00220972
+	0xa7f984c5	0xb4eeae8a	0x11718517	0x06e70840
+	0xb3091fe5	0x099ccb1a	0xac3df88c	0xa8bd0ca3
+	0xa202bbc0	0x19979cf1	0x8656c385	0x139abf7b
+	0xae298ea4	0xab9481ae	0xe08e2c38	0x27967dab
+	0x1108054c	0x1ba0d3c5	0x8a0fb923	0x9c54f682
+	0x5f363a46	0xec564b34	0x8d53c918	0x47f39642
+	0x3fd68743	0x197f16cc	0x2b03d11c	0xcc574d53
+	0x8b2d1aa3	0xd403c5b0	0xce21d3a6	0x57c88abe
+	0x56d6b12b	0x204f9ac8	0xfd44c338	0x18417de6
+	0x5582f0bf	0x7ea9d04f	0x7bdee65d	0x9fe3f5b5
+	0xa14edd82	0x8301f6ba	0x24bc737a	0x5c6e71a8
+	0xdb0d7fc2	0x243b6e99	0x3941f113	0xcaaa3674
+	0x1b25b686	0xfb219a33	0x1b122757	0x27298223
+	0x44cbb8ad	0xed4e6ef9	0xae338c2d	0xa8d231ee
+	0x9bc2d8f3	0xcecd4d27	0xe8ba9908	0x9a106344
+	0xbdf27147	0x0c547009	0x46b16833	0xd89b0690
+	0x4b742f40	0x733d4cd5	0x1abb6f77	0x803f40df
+	0xf8d909bb	0x8fa6a921	0x08966531	0xdf093174
+	0xc7ee92c8	0x4272612d	0x149f8242	0xf8c07ec3
+	0x99259781	0x8bf3f9c0	0x09d6b679	0x19a1968f
+	0x735b197e	0xa98c913f	0x3e208a56	0x59b2b40b
+	0x0ed212ed	0xfc92d02a	0xe9b1b441	0x1429fc3c
+	0x8a6fb38c	0x6235d73e	0x82f5aca8	0x9ebb490a
+	0x718fed05	0xee355cdc	0xf34bbc8e	0xcfde74ac
+	0x5c267a70	0x30b66c7f	0x9a655781	0x1d354268
+	0xd0debf01	0x71798948	0x4542b707	0x66c02ecf
+	0x49763e11	0xa02f170b	0xbcf30ee9	0xba9bbfec
+	0x6d915d18	0xcadd484f	0x8eadbd10	0x91463818
+	0xe8add34f	0x55620c30	0x14d47fa5	0x63c2a25f
+	0x7213f2f4	0x6d96a516	0xf10f4ed1	0x9825aeac
+	0xe9ca9b8a	0x4bb0e2aa	0x957f8851	0x1a41de29
+	0xa0039e6c	0x3ec63393	0x66b6ac8a	0x2992d983
+	0x2d73caa4	0xb0ae06c2	0xa4008915	0x2ba7050d
+	0x6d9e01e6	0x908f316f	0x3f17dabb	0x8c86b0e3
+	0x89fcebf8	0xbada4307	0x0f6e9f6f	0x07f36992
+	0x1a82520e	0x728f11a9	0x418aa9b7	0xc57f51d7
+	0xcffa1cd0	0xf9f6d902	0xdf22329a	0x4ac48293
+	0x37326e23	0xbb39c187	0xc9086dfe	0x1347e4f8
+	0x7ae88ecb	0xc280a07f	0x7f0a6b0a	0x57cff37d
+	0x2dfd629d	0x5a8a444d	0x934bcafb	0x593b6a3a
+	0x9c62c1ca	0x0ecdb2dc	0xb4c2fd82	0x2c19c0ab
+	0x26acf079	0x71aa1041	0x8aeb2595	0xed90f704
+	0x7d68f5c5	0x624429d5	0xefd0d147	0xc8682f79
+	0xfe7e9cc0	0xaee6c970	0x33e9231e	0x4720df4d
+	0x6a3f6428	0x463b676f	0x71960ee6	0xc684d974
+	0x9f01a6d2	0x728cbec7	0x2e20d715	0x172a4a11
+	0x4153ad1e	0xb1f36e53	0xc277f818	0x94ac6d39
+	0x502f91d8	0x3028b1ee	0x48390347	0x45a8b5af
+	0x2cb8095f	0x063cbe4a	0x07a53b3b	0xcfd08c80
+	0x81679803	0x9fa4726a	0xa682f4c8	0x4d90e8bf
+	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 60bd05afb6..936455b5e5 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -117,6 +117,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -297,10 +298,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5d601b3444..0d462a9c78 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -69,6 +69,8 @@
 			irq-router {
 				compatible = "intel,irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-8bit;
+				intel,actl-addr = <0x44>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0x0e40>;
 				intel,pirq-routing = <
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
deleted file mode 100644
index 4872b92860..0000000000
--- a/arch/x86/include/asm/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG		"RSD PTR "  /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"U-BootAC"  /* Must be exactly 8 bytes long! */
-#define OEM_ID			"U-Boot"    /* Must be exactly 6 bytes long! */
-#define ASLC			"U-Bo"      /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000000..8e7b603ba0
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,
+	    , 8,
+	CLCR, 8,
+	CMCR, 8,
+	CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+	Store(0x83, CLCR)
+	Store(0x01, CDAT)	/* 115200 baud (low) */
+	Store(0x00, CDLM)	/* 115200 baud (high) */
+	Store(0x03, CLCR)	/* word=8 stop=1 parity=none */
+	Store(0x03, CMCR)	/* DTR=1 RTS=1 out1/2=Off loop=Off */
+	Store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+	And(CLSR, 0x20, Local0)
+	While (LEqual(Local0, Zero)) {
+		And(CLSR, 0x20, Local0)
+	}
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+	THRE()
+	Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+	If (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+	And(Arg0, 0x0f, Local0)
+	If (LLess(Local0, 10)) {
+		Add(Local0, 0x30, Local0)
+	} Else {
+		Add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+	If (LEqual(ObjectType(Arg0), 1)) {
+		If (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} Else {
+			If (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} Else {
+				DBGB(Arg0)
+			}
+		}
+	} Else {
+		Name(BDBG, Buffer(80) {})
+		Store(Arg0, BDBG)
+		Store(0, Local1)
+		While (One) {
+			Store(GETC(BDBG, Local1), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (Zero)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+
+	Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000000..46381b687e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+	If (LLess(Arg0, Arg1)) {
+		Return (Arg0)
+	} Else {
+		Return (Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While (LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		If (LGreater(Local2, Local3)) {
+			Return (One)
+		} Else {
+			If (LLess(Local2, Local3)) {
+				Return (Ones)
+			}
+		}
+		Increment(Local4)
+	}
+
+	If (LLess(Local4, Local5)) {
+		Return (One)
+	} Else {
+		If (LLess(Local4, Local6)) {
+			Return (Ones)
+		} Else {
+			Return (Zero)
+		}
+	}
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return (Zero)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While (LLess(Local2, Local3)) {
+		If (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return (Zero)
+		}
+		Increment(Local2)
+	}
+
+	Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	If (LNotEqual(Arg0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, Arg0, Local0)
+	}
+
+	Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000000..e8cff100fc
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING		0x00
+#define STA_PRESENT		0x01
+#define STA_ENABLED		0x03
+#define STA_DISABLED		0x09
+#define STA_INVISIBLE		0x0b
+#define STA_UNAVAILABLE		0x0d
+#define STA_VISIBLE		0x0f
+
+/* SMBus status codes */
+#define SMB_OK			0x00
+#define SMB_UNKNOWN_FAIL	0x07
+#define SMB_DEV_ADDR_NAK	0x10
+#define SMB_DEVICE_ERROR	0x11
+#define SMB_DEV_CMD_DENIED	0x12
+#define SMB_UNKNOWN_ERR		0x13
+#define SMB_DEV_ACC_DENIED	0x17
+#define SMB_TIMEOUT		0x18
+#define SMB_HST_UNSUPP_PROTOCOL	0x19
+#define SMB_BUSY		0x1a
+#define SMB_PKT_CHK_ERROR	0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK	0x00
+#define NOTIFY_DEVICE_CHECK	0x01
+#define NOTIFY_DEVICE_WAKE	0x02
+#define NOTIFY_EJECT_REQUEST	0x03
+#define NOTIFY_DEVICE_CHECK_JR	0x04
+#define NOTIFY_FREQUENCY_ERROR	0x05
+#define NOTIFY_BUS_MODE		0x06
+#define NOTIFY_POWER_FAULT	0x07
+#define NOTIFY_CAPABILITIES	0x08
+#define NOTIFY_PLD_CHECK	0x09
+#define NOTIFY_SLIT_UPDATE	0x0b
+#define NOTIFY_SRA_UPDATE	0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG	0x80
+#define NOTIFY_BAT_INFOCHG	0x81
+#define NOTIFY_BAT_MAINTDATA	0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG	0x80
+#define NOTIFY_PWR_INFOCHG	0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG	0x80
+#define NOTIFY_TZ_TRIPPTCHG	0x81
+#define NOTIFY_TZ_DEVLISTCHG	0x82
+#define NOTIFY_TZ_RELTBLCHG	0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON	0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON	0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG	0x80
+#define NOTIFY_CPU_CSTATECHG	0x81
+#define NOTIFY_CPU_THROTLCHG	0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG	0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG	0x80
+#define NOTIFY_ALS_COLORTMPCHG	0x81
+#define NOTIFY_ALS_RESPCHG	0x82
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9856fa6c43..56aa282127 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -2,83 +2,19 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
-#define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
-#define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */
-#define ASLC			"INTL"		/* Must be 4 bytes long! */
-
-#define OEM_REVISION	42
-#define ASL_COMPILER_REVISION	42
-
-/* IO ports to generate SMIs */
-#define APM_CNT			0xb2
-#define APM_CNT_CST_CONTROL	0x85
-#define APM_CNT_PST_CONTROL	0x80
-#define APM_CNT_ACPI_DISABLE	0x1e
-#define APM_CNT_ACPI_ENABLE	0xe1
-#define APM_CNT_MBI_UPDATE	0xeb
-#define APM_CNT_GNVS_UPDATE	0xea
-#define APM_CNT_FINALIZE	0xcb
-#define APM_CNT_LEGACY		0xcc
-#define APM_ST			0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT	0x0
-#define MP_IRQ_POLARITY_HIGH	0x1
-#define MP_IRQ_POLARITY_LOW	0x3
-#define MP_IRQ_POLARITY_MASK	0x3
-#define MP_IRQ_TRIGGER_DEFAULT	0x0
-#define MP_IRQ_TRIGGER_EDGE	0x4
-#define MP_IRQ_TRIGGER_LEVEL	0xc
-#define MP_IRQ_TRIGGER_MASK	0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL		0x00
-#define SCIS_MASK	0x07
-#define SCIS_IRQ9	0x00
-#define SCIS_IRQ10	0x01
-#define SCIS_IRQ11	0x02
-#define SCIS_IRQ20	0x04
-#define SCIS_IRQ21	0x05
-#define SCIS_IRQ22	0x06
-#define SCIS_IRQ23	0x07
-
-#define ACPI_REV_ACPI_1_0	1
-#define ACPI_REV_ACPI_2_0	1
-#define ACPI_REV_ACPI_3_0	2
-#define ACPI_REV_ACPI_4_0	3
-#define ACPI_REV_ACPI_5_0	5
+#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
+#define OEM_ID			"U-BOOT"	/* U-Boot */
+#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
+#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
 #define ACPI_RSDP_REV_ACPI_1_0	0
 #define ACPI_RSDP_REV_ACPI_2_0	2
 
-typedef struct acpi_gen_regaddr {
-	u8  space_id;	/* Address space ID */
-	u8  bit_width;	/* Register size in bits */
-	u8  bit_offset;	/* Register bit offset */
-	union {
-		/* Reserved in ACPI 2.0 - 2.0b */
-		u8  resv;
-		/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-		u8  access_size;
-	};
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-} acpi_addr_t;
-
-
 /*
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -87,7 +23,7 @@ struct acpi_rsdp {
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
-	u8 revision;		/* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+	u8 revision;		/* 0 for ACPI 1.0, others 2 */
 	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
 	u32 length;		/* Total RSDP length (incl. extended part) */
 	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
@@ -95,35 +31,8 @@ struct acpi_rsdp {
 	u8 reserved[3];
 };
 
-enum acpi_address_space_type {
-	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
-	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
-	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
-	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
-	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
-	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
-	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
-};
-
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL	1	/* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT	1	/* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT	2	/* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD	1	/* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS	2	/* BM_STS avoidance bit */
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
-	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */
-	ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
-	ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
-	ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
-	ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
-
 /* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
 	char signature[4];	/* ACPI signature (4 ASCII characters) */
 	u32 length;		/* Table length in bytes (incl. header) */
 	u8 revision;		/* Table version (not ACPI version!) */
@@ -131,12 +40,12 @@ typedef struct acpi_table_header {
 	char oem_id[6];		/* OEM identification */
 	char oem_table_id[8];	/* OEM table identification */
 	u32 oem_revision;	/* OEM revision number */
-	char asl_compiler_id[4]; /* ASL compiler vendor ID */
-	u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+	char aslc_id[4];	/* ASL compiler vendor ID */
+	u32 aslc_revision;	/* ASL compiler revision number */
+};
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES	32
+#define MAX_ACPI_TABLES		32
 
 /* RSDT (Root System Description Table) */
 struct acpi_rsdt {
@@ -150,103 +59,80 @@ struct acpi_xsdt {
 	u64 entry[MAX_ACPI_TABLES];
 };
 
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
-	struct acpi_table_header header;
-	u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
-	u32 base_address;
-	u32 base_reserved;
-	u16 pci_segment_group_number;
-	u8 start_bus_number;
-	u8 end_bus_number;
-	u8 reserved[4];
-};
-
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
-	struct acpi_table_header header;
-	u32 lapic_addr;			/* Local APIC address */
-	u32 flags;			/* Multiple APIC flags */
-} acpi_madt_t;
-
-enum dev_scope_type {
-	SCOPE_PCI_ENDPOINT = 1,
-	SCOPE_PCI_SUB = 2,
-	SCOPE_IOAPIC = 3,
-	SCOPE_MSI_HPET = 4
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
 };
 
-typedef struct dev_scope {
-	u8 type;
-	u8 length;
-	u8 reserved[2];
-	u8 enumeration;
-	u8 start_bus;
-	struct {
-		u8 dev;
-		u8 fn;
-	} path[0];
-} __packed dev_scope_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
-	LOCALAPIC	= 0,	/* Processor local APIC */
-	IOAPIC,			/* I/O APIC */
-	IRQSOURCEOVERRIDE,	/* Interrupt source override */
-	NMITYPE,		/* NMI source */
-	LOCALNMITYPE, 		/* Local APIC NMI */
-	LAPICADDRESSOVERRIDE,	/* Local APIC address override */
-	IOSAPIC,		/* I/O SAPIC */
-	LOCALSAPIC,		/* Local SAPIC */
-	PLATFORMIRQSOURCES,	/* Platform interrupt sources */
-	LOCALX2SAPIC,		/* Processor local x2APIC */
-	LOCALX2APICNMI,		/* Local x2APIC NMI */
-};
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED	101
+#define ACPI_FADT_C3_NOT_SUPPORTED	1001
 
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
-	u8 type;		/* Type (0) */
-	u8 length;		/* Length in bytes (8) */
-	u8 processor_id;	/* ACPI processor ID */
-	u8 apic_id;		/* Local APIC ID */
-	u32 flags;		/* Local APIC flags */
-};
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE		0x00
+#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
+#define ACPI_FADT_8042			(1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
 
-#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT		(1 << 0)
-/* bits 1-31: reserved */
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD		(1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
+#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
+#define ACPI_FADT_POWER_BUTTON		(1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
+#define ACPI_FADT_FIXED_RTC		(1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
+#define ACPI_FADT_32BIT_TIMER		(1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
+#define ACPI_FADT_RESET_REGISTER	(1 << 10)
+#define ACPI_FADT_SEALED_CASE		(1 << 11)
+#define ACPI_FADT_HEADLESS		(1 << 12)
+#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
+#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
+#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
 
-/* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
-	u8 type;		/* Type (4) */
-	u8 length;		/* Length in bytes (6) */
-	u8 processor_id;	/* ACPI processor ID */
-	u16 flags;		/* MPS INTI flags */
-	u8 lint;		/* Local APIC LINT# */
+enum acpi_address_space_type {
+	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
+	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
+	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
+	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
+	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
+	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
+	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
 };
 
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
-	u8 type;		/* Type (1) */
-	u8 length;		/* Length in bytes (12) */
-	u8 ioapic_id;		/* I/O APIC ID */
-	u8 reserved;
-	u32 ioapic_addr;	/* I/O APIC address */
-	u32 gsi_base;		/* Global system interrupt base */
+enum acpi_address_space_size {
+	ACPI_ACCESS_SIZE_UNDEFINED = 0,
+	ACPI_ACCESS_SIZE_BYTE_ACCESS,
+	ACPI_ACCESS_SIZE_WORD_ACCESS,
+	ACPI_ACCESS_SIZE_DWORD_ACCESS,
+	ACPI_ACCESS_SIZE_QWORD_ACCESS
 };
 
-/* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
-	u8 type;		/* Type (2) */
-	u8 length;		/* Length in bytes (10) */
-	u8 bus;			/* ISA (0) */
-	u8 source;		/* Bus-relative int. source (IRQ) */
-	u32 gsirq;		/* Global system interrupt */
-	u16 flags;		/* MPS INTI flags */
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
 };
 
 /* FADT (Fixed ACPI Description Table) */
@@ -254,7 +140,7 @@ struct __packed acpi_fadt {
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 model;
+	u8 res1;
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;
@@ -309,85 +195,121 @@ struct __packed acpi_fadt {
 	struct acpi_gen_regaddr x_gpe1_blk;
 };
 
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED	101
-#define ACPI_FADT_C3_NOT_SUPPORTED	1001
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F	(1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
 
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD		(1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
-#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
-#define ACPI_FADT_POWER_BUTTON		(1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
-#define ACPI_FADT_FIXED_RTC		(1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
-#define ACPI_FADT_32BIT_TIMER		(1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
-#define ACPI_FADT_RESET_REGISTER	(1 << 10)
-#define ACPI_FADT_SEALED_CASE		(1 << 11)
-#define ACPI_FADT_HEADLESS		(1 << 12)
-#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
-#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
-#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+	char signature[4];		/* "FACS" */
+	u32 length;			/* Length in bytes (>= 64) */
+	u32 hardware_signature;		/* Hardware signature */
+	u32 firmware_waking_vector;	/* Firmware waking vector */
+	u32 global_lock;		/* Global lock */
+	u32 flags;			/* FACS flags */
+	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
+	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
+	u8 version;			/* Version 2 */
+	u8 res1[3];
+	u32 ospm_flags;			/* OSPM enabled flags */
+	u8 res2[24];
+};
 
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
-#define ACPI_FADT_8042			(1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE		0x00
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
 
-/* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED		0
-#define PM_DESKTOP		1
-#define PM_MOBILE		2
-#define PM_WORKSTATION		3
-#define PM_ENTERPRISE_SERVER	4
-#define PM_SOHO_SERVER		5
-#define PM_APPLIANCE_PC		6
-#define PM_PERFORMANCE_SERVER	7
-#define PM_TABLET		8	/* ACPI 5.0 */
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+	struct acpi_table_header header;
+	u32 lapic_addr;			/* Local APIC address */
+	u32 flags;			/* Multiple APIC flags */
+};
 
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
-	char signature[4];			/* "FACS" */
-	u32 length;				/* Length in bytes (>= 64) */
-	u32 hardware_signature;			/* Hardware signature */
-	u32 firmware_waking_vector;		/* Firmware waking vector */
-	u32 global_lock;			/* Global lock */
-	u32 flags;				/* FACS flags */
-	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
-	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
-	u8 version;				/* ACPI 4.0: 2 */
-	u8 resv[31];				/* FIXME: 4.0: ospm_flags */
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
 };
 
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F	(1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
-/* Bits 31..2: reserved */
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
+
+struct acpi_madt_lapic {
+	u8 type;		/* Type (0) */
+	u8 length;		/* Length in bytes (8) */
+	u8 processor_id;	/* ACPI processor ID */
+	u8 apic_id;		/* Local APIC ID */
+	u32 flags;		/* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+	u8 type;		/* Type (1) */
+	u8 length;		/* Length in bytes (12) */
+	u8 ioapic_id;		/* I/O APIC ID */
+	u8 reserved;
+	u32 ioapic_addr;	/* I/O APIC address */
+	u32 gsi_base;		/* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+	u8 type;		/* Type (2) */
+	u8 length;		/* Length in bytes (10) */
+	u8 bus;			/* ISA (0) */
+	u8 source;		/* Bus-relative int. source (IRQ) */
+	u32 gsirq;		/* Global system interrupt */
+	u16 flags;		/* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+	u8 type;		/* Type (4) */
+	u8 length;		/* Length in bytes (6) */
+	u8 processor_id;	/* ACPI processor ID */
+	u16 flags;		/* MPS INTI flags */
+	u8 lint;		/* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+	u32 base_address_l;
+	u32 base_address_h;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN		(1 << 0)
 
 /* These can be used by the target port */
 
-unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base);
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags);
-unsigned long acpi_fill_madt(unsigned long current);
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-			 void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
-			 u16 flags, u8 lint);
+		      void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000000..ef340f3d7b
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 1)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 2)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 3)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
new file mode 100644
index 0000000000..2c3585ac7f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
new file mode 100644
index 0000000000..0affa2335c
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -0,0 +1,493 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
new file mode 100644
index 0000000000..64d38207d9
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000000..d7463140f1
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,	A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, PCIE_DEV,	A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000000..385671c968
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
+	#include "irqlinks.asl"
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			/*
+			 * TODO:
+			 *
+			 * Need to hide the internal UART depending on whether
+			 * internal UART is enabled or not so that external
+			 * SuperIO UART can be exposed to system.
+			 */
+			Store(1, UI3E)
+			Store(1, UI4E)
+			Store(1, C1EN)
+			Return (STA_VISIBLE)
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			/*
+			 * Disable as Windows doesn't like it, and systems
+			 * don't seem to use it
+			 */
+			/* IRQNoFlags() { 8 } */
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000000..6bc82ecfe1
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+
+	/* ACPI devices */
+	#include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000000..eb5ae76186
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000000..34d3951424
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+
+		/* High PCI Memory Region */
+		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , UMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Update High PCI resource area */
+		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+		/* Set base address to 48GB and allocate 16GB for PCI space */
+		Store(0xc00000000, UMIN)
+		Store(0x400000000, ULEN)
+		Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* USB EHCI 0:1d.0 */
+	#include "usb.asl"
+
+	/* USB XHCI 0:14.0 */
+	#include "xhci.asl"
+
+	/* IRQ routing for each PCI device */
+	#include "irqroute.asl"
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000000..311f471843
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 4 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 2)
+
+	/* Highest D state in S4 state */
+	Name(_S4D, 2)
+
+	Device (HUB7)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device(PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device(PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device(PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device(PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000000..a5a4404651
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name(_ADR, 0x00140000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 3 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 3)
+
+	Device (RHUB)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device (PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device (PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device (PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device (PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000000..798d35bccf
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV		0x00
+
+/* Graphics and Display */
+#define GFX_DEV		0x02
+
+/* MIPI */
+#define MIPI_DEV	0x03
+
+/* EMMC Port */
+#define EMMC_DEV	0x10
+
+/* SDIO Port */
+#define SDIO_DEV	0x11
+
+/* SD Port */
+#define SD_DEV		0x12
+
+/* SATA */
+#define SATA_DEV	0x13
+
+/* xHCI */
+#define XHCI_DEV	0x14
+
+/* LPE Audio */
+#define LPE_DEV		0x15
+
+/* OTG */
+#define OTG_DEV		0x16
+
+/* MMC45 Port */
+#define MMC45_DEV	0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV	0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV		0x1a
+
+/* HD Audio */
+#define HDA_DEV		0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV	0x1c
+
+/* EHCI */
+#define EHCI_DEV	0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV	0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV		0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000000..62a91051e4
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS		0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS		0xfeb00000
+#define ABORT_BASE_SIZE			0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SPI_BASE_SIZE			0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS		0xfed03000
+#define PMC_BASE_SIZE			0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS		0xfed05000
+#define PUNIT_BASE_SIZE			0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS		0xfed08000
+#define ILB_BASE_SIZE			0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		0xfed1c000
+#define RCBA_BASE_SIZE			0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS		0xfef00000
+#define MPHY_BASE_SIZE			0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS		0x0400
+#define ACPI_BASE_SIZE			0x80
+
+#define GPIO_BASE_ADDRESS		0x0500
+#define GPIO_BASE_SIZE			0x100
+
+#define SMBUS_BASE_ADDRESS		0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000000..cd66f83c41
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ			16
+#define PIRQB_APIC_IRQ			17
+#define PIRQC_APIC_IRQ			18
+#define PIRQD_APIC_IRQ			19
+#define PIRQE_APIC_IRQ			20
+#define PIRQF_APIC_IRQ			21
+#define PIRQG_APIC_IRQ			22
+#define PIRQH_APIC_IRQ			23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ			24
+#define LPE_DMA1_IRQ			25
+#define LPE_SSP0_IRQ			26
+#define LPE_SSP1_IRQ			27
+#define LPE_SSP2_IRQ			28
+#define LPE_IPC2HOST_IRQ		29
+#define LPSS_I2C1_IRQ			32
+#define LPSS_I2C2_IRQ			33
+#define LPSS_I2C3_IRQ			34
+#define LPSS_I2C4_IRQ			35
+#define LPSS_I2C5_IRQ			36
+#define LPSS_I2C6_IRQ			37
+#define LPSS_I2C7_IRQ			38
+#define LPSS_HSUART1_IRQ		39
+#define LPSS_HSUART2_IRQ		40
+#define LPSS_SPI_IRQ			41
+#define LPSS_DMA1_IRQ			42
+#define LPSS_DMA2_IRQ			43
+#define SCC_EMMC_IRQ			44
+#define SCC_SDIO_IRQ			46
+#define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9be6c..e036f744f6 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -295,6 +295,25 @@ struct cbmem_entry {
 #define CBMEM_ID_NONE			0x00000000
 
 /**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return:	always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes:	size of configuration table to be allocated
+ * @return:	pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
  * write_coreboot_table() - write coreboot table
  *
  * This writes coreboot table at a given address.
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac24cf..7434f779b6 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@ struct arch_global_data {
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+	u32 high_table_ptr;
+	u32 high_table_limit;
+#endif
 };
 
 #endif
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 5b9e673763..ddb529e581 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -34,6 +34,8 @@ enum pirq_config {
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address
+ * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr:	ACTL register offset
  */
 struct irq_router {
 	int config;
@@ -41,6 +43,8 @@ struct irq_router {
 	u16 irq_mask;
 	u32 bdf;
 	u32 ibase;
+	bool actl_8bit;
+	int actl_addr;
 };
 
 struct pirq_routing {
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index dc90df2050..e17f0bb0f2 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,7 @@ obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
-obj-y	+= coreboot_table.o
+obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
@@ -31,7 +31,7 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o
 obj-y += sfi.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
 obj-y	+= string.o
-ifndef CONFIG_QEMU_ACPI_TABLE
+ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 790f6fbd0f..ffb4678e51 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -2,6 +2,7 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -10,25 +11,92 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
-#include <dm/lists.h>
 #include <asm/acpi_table.h>
-#include <asm/cpu.h>
-#include <asm/ioapic.h>
+#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
-#include <asm/pci.h>
 
 /*
- * IASL compiles the dsdt entries and
- * writes the hex values to AmlCode array.
- * CamelCase cannot be handled here.
+ * IASL compiles the dsdt entries and writes the hex values
+ * to a C array AmlCode[] (see dsdt.c).
  */
 extern const unsigned char AmlCode[];
 
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = (u32)rsdt;
+
+	/*
+	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+	 *
+	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+	 * revision 0)
+	 */
+	if (xsdt == NULL) {
+		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+	} else {
+		rsdp->xsdt_address = (u64)(u32)xsdt;
+		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+	}
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+			sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &(rsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)rsdt,
+			sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &(xsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)xsdt,
+			sizeof(struct acpi_xsdt));
+}
+
 /**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
 static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 {
 	int i, entries_num;
@@ -50,7 +118,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 
 	if (i >= entries_num) {
-		debug("ACPI: Error: too many tables.\n");
+		debug("ACPI: Error: too many tables\n");
 		return;
 	}
 
@@ -58,12 +126,13 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	rsdt->entry[i] = (u32)table;
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
-	rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+	rsdt->header.length = sizeof(struct acpi_table_header) +
+				(sizeof(u32) * (i + 1));
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
 	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-						       rsdt->header.length);
+			rsdt->header.length);
 
 	/*
 	 * And now the same thing for the XSDT. We use the same index as for
@@ -74,8 +143,8 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 		xsdt->entry[i] = (u64)(u32)table;
 
 		/* Fix XSDT length */
-		xsdt->header.length = sizeof(acpi_header_t) +
-			 (sizeof(u64) * (i + 1));
+		xsdt->header.length = sizeof(struct acpi_table_header) +
+			(sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum */
 		xsdt->header.checksum = 0;
@@ -84,38 +153,56 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 }
 
+static void acpi_create_facs(struct acpi_facs *facs)
+{
+	memset((void *)facs, 0, sizeof(struct acpi_facs));
+
+	memcpy(facs->signature, "FACS", 4);
+	facs->length = sizeof(struct acpi_facs);
+	facs->hardware_signature = 0;
+	facs->firmware_waking_vector = 0;
+	facs->global_lock = 0;
+	facs->flags = 0;
+	facs->x_firmware_waking_vector_l = 0;
+	facs->x_firmware_waking_vector_h = 0;
+	facs->version = 1;
+}
+
 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
-			 u8 cpu, u8 apic)
+				  u8 cpu, u8 apic)
 {
-	lapic->type = LOCALAPIC; /* Local APIC structure */
+	lapic->type = ACPI_APIC_LAPIC;
 	lapic->length = sizeof(struct acpi_madt_lapic);
-	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
+	lapic->flags = LOCAL_APIC_FLAG_ENABLED;
 	lapic->processor_id = cpu;
 	lapic->apic_id = apic;
 
 	return lapic->length;
 }
 
-unsigned long acpi_create_madt_lapics(unsigned long current)
+int acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
+	int length = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 
-		current += acpi_create_madt_lapic(
+		length += acpi_create_madt_lapic(
 			(struct acpi_madt_lapic *)current,
 			plat->cpu_id, plat->cpu_id);
-		}
-		return current;
+		current += length;
+	}
+
+	return length;
 }
 
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base)
 {
-	ioapic->type = IOAPIC;
+	ioapic->type = ACPI_APIC_IOAPIC;
 	ioapic->length = sizeof(struct acpi_madt_ioapic);
 	ioapic->reserved = 0x00;
 	ioapic->gsi_base = gsi_base;
@@ -126,9 +213,9 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 }
 
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags)
+				 u8 bus, u8 source, u32 gsirq, u16 flags)
 {
-	irqoverride->type = IRQSOURCEOVERRIDE;
+	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
 	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
 	irqoverride->bus = bus;
 	irqoverride->source = source;
@@ -139,9 +226,9 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 }
 
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
-			 u8 cpu, u16 flags, u8 lint)
+			       u8 cpu, u16 flags, u8 lint)
 {
-	lapic_nmi->type = LOCALNMITYPE;
+	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
 	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
 	lapic_nmi->flags = flags;
 	lapic_nmi->processor_id = cpu;
@@ -150,45 +237,35 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 	return lapic_nmi->length;
 }
 
-static void fill_header(acpi_header_t *header, char *signature, int length)
-{
-	memcpy(header->signature, signature, length);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-}
-
 static void acpi_create_madt(struct acpi_madt *madt)
 {
-	acpi_header_t *header = &(madt->header);
-	unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
+	struct acpi_table_header *header = &(madt->header);
+	u32 current = (u32)madt + sizeof(struct acpi_madt);
 
 	memset((void *)madt, 0, sizeof(struct acpi_madt));
 
 	/* Fill out header fields */
-	fill_header(header, "APIC", 4);
+	acpi_fill_header(header, "APIC");
 	header->length = sizeof(struct acpi_madt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 4;
 
 	madt->lapic_addr = LAPIC_DEFAULT_BASE;
-	madt->flags = PCAT_COMPAT;
+	madt->flags = ACPI_MADT_PCAT_COMPAT;
 
 	current = acpi_fill_madt(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)madt;
+	header->length = current - (u32)madt;
 
 	header->checksum = table_compute_checksum((void *)madt, header->length);
 }
 
 static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
-			 u32 base, u16 seg_nr, u8 start, u8 end)
+				     u32 base, u16 seg_nr, u8 start, u8 end)
 {
 	memset(mmconfig, 0, sizeof(*mmconfig));
-	mmconfig->base_address = base;
-	mmconfig->base_reserved = 0;
+	mmconfig->base_address_l = base;
+	mmconfig->base_address_h = 0;
 	mmconfig->pci_segment_group_number = seg_nr;
 	mmconfig->start_bus_number = start;
 	mmconfig->end_bus_number = end;
@@ -196,11 +273,11 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
 	return sizeof(struct acpi_mcfg_mmconfig);
 }
 
-static unsigned long acpi_fill_mcfg(unsigned long current)
+static u32 acpi_fill_mcfg(u32 current)
 {
 	current += acpi_create_mcfg_mmconfig
 		((struct acpi_mcfg_mmconfig *)current,
-		 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+		CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
 
 	return current;
 }
@@ -208,132 +285,45 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 /* MCFG is defined in the PCI Firmware Specification 3.0 */
 static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 {
-	acpi_header_t *header = &(mcfg->header);
-	unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
+	struct acpi_table_header *header = &(mcfg->header);
+	u32 current = (u32)mcfg + sizeof(struct acpi_mcfg);
 
 	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
 
 	/* Fill out header fields */
-	fill_header(header, "MCFG", 4);
+	acpi_fill_header(header, "MCFG");
 	header->length = sizeof(struct acpi_mcfg);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 1;
 
 	current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)mcfg;
+	header->length = current - (u32)mcfg;
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
-static void acpi_create_facs(struct acpi_facs *facs)
-{
-	memset((void *)facs, 0, sizeof(struct acpi_facs));
-
-	memcpy(facs->signature, "FACS", 4);
-	facs->length = sizeof(struct acpi_facs);
-	facs->hardware_signature = 0;
-	facs->firmware_waking_vector = 0;
-	facs->global_lock = 0;
-	facs->flags = 0;
-	facs->x_firmware_waking_vector_l = 0;
-	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
-	acpi_header_t *header = &(rsdt->header);
-
-	/* Fill out header fields */
-	fill_header(header, "RSDT", 4);
-	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+static void enter_acpi_mode(int pm1_cnt)
 {
-	acpi_header_t *header = &(xsdt->header);
-
-	/* Fill out header fields */
-	fill_header(header, "XSDT", 4);
-	header->length = sizeof(struct acpi_xsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			 struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
 	/*
-	* Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	*
-	* Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	* If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	* revision 0)
-	*/
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
-	}
-
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
-}
-
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
-			 const char *oem_table_id)
-{
-	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
-
-	memset((void *)ssdt, 0, sizeof(acpi_header_t));
-
-	memcpy(&ssdt->signature, "SSDT", 4);
-	/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-	ssdt->revision = ACPI_REV_ACPI_3_0;
-	memcpy(&ssdt->oem_id, OEM_ID, 6);
-	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
-	ssdt->oem_revision = OEM_REVISION;
-	memcpy(&ssdt->asl_compiler_id, ASLC, 4);
-	ssdt->asl_compiler_revision = ASL_COMPILER_REVISION;
-	ssdt->length = sizeof(acpi_header_t);
-
-	/* (Re)calculate length and checksum */
-	ssdt->length = current - (unsigned long)ssdt;
-	ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+	 * PM1_CNT register bit0 selects the power management event to be
+	 * either an SCI or SMI interrupt. When this bit is set, then power
+	 * management events will generate an SCI interrupt. When this bit
+	 * is reset power management events will generate an SMI interrupt.
+	 *
+	 * Per ACPI spec, it is the responsibility of the hardware to set
+	 * or reset this bit. OSPM always preserves this bit position.
+	 *
+	 * U-Boot does not support SMI. And we don't have plan to support
+	 * anything running in SMM within U-Boot. To create a legacy-free
+	 * system, and expose ourselves to OSPM as working under ACPI mode
+	 * already, turn this bit on.
+	 */
+	outw(PM1_CNT_SCI_EN, pm1_cnt);
 }
 
 /*
  * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/fw_cfg.c
+ * arch/x86/cpu/qemu/acpi_table.c
  */
 u32 write_acpi_tables(u32 start)
 {
@@ -342,18 +332,17 @@ u32 write_acpi_tables(u32 start)
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
 	struct acpi_facs *facs;
-	acpi_header_t *dsdt;
+	struct acpi_table_header *dsdt;
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
-	acpi_header_t *ssdt;
 
 	current = start;
 
-	/* Align ACPI tables to 16byte */
+	/* Align ACPI tables to 16 byte */
 	current = ALIGN(current, 16);
 
-	debug("ACPI: Writing ACPI tables at %lx.\n", start);
+	debug("ACPI: Writing ACPI tables at %x\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (struct acpi_rsdp *)current;
@@ -364,7 +353,11 @@ u32 write_acpi_tables(u32 start)
 	current = ALIGN(current, 16);
 	xsdt = (struct acpi_xsdt *)current;
 	current += sizeof(struct acpi_xsdt);
-	current = ALIGN(current, 16);
+	/*
+	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+	 * boundary (Windows checks this, but Linux does not).
+	 */
+	current = ALIGN(current, 64);
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
@@ -381,21 +374,13 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_facs(facs);
 
 	debug("ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *)current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	if (dsdt->length >= sizeof(acpi_header_t)) {
-		current += sizeof(acpi_header_t);
-		memcpy((char *)current,
-				(char *)&AmlCode + sizeof(acpi_header_t),
-				dsdt->length - sizeof(acpi_header_t));
-		current += dsdt->length - sizeof(acpi_header_t);
-
-		/* (Re)calculate length and checksum */
-		dsdt->length = current - (unsigned long)dsdt;
-		dsdt->checksum = 0;
-		dsdt->checksum = table_compute_checksum((void *)dsdt,
-				dsdt->length);
-	}
+	dsdt = (struct acpi_table_header *)current;
+	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
+	current += sizeof(struct acpi_table_header);
+	memcpy((char *)current,
+	       (char *)&AmlCode + sizeof(struct acpi_table_header),
+	       dsdt->length - sizeof(struct acpi_table_header));
+	current += dsdt->length - sizeof(struct acpi_table_header);
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * FADT\n");
@@ -405,36 +390,29 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
-	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
-
 	debug("ACPI:    * MADT\n");
 	madt = (struct acpi_madt *)current;
 	acpi_create_madt(madt);
-	if (madt->header.length > sizeof(struct acpi_madt)) {
-		current += madt->header.length;
-		acpi_add_table(rsdp, madt);
-	}
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
 	current = ALIGN(current, 16);
 
-	debug("ACPI:    * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	if (ssdt->length > sizeof(acpi_header_t)) {
-		current += ssdt->length;
-		acpi_add_table(rsdp, ssdt);
-		current = ALIGN(current, 16);
-	}
+	debug("ACPI:    * MCFG\n");
+	mcfg = (struct acpi_mcfg *)current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+	current = ALIGN(current, 16);
+
+	debug("current = %x\n", current);
 
-	debug("current = %lx\n", current);
+	debug("ACPI: done\n");
 
-	debug("ACPI: done.\n");
+	/*
+	 * Other than waiting for OSPM to request us to switch to ACPI mode,
+	 * do it by ourselves, since SMI will not be triggered.
+	 */
+	enter_acpi_mode(fadt->pm1a_cnt_blk);
 
 	return current;
 }
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 783be691af..7cf9de4d7b 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -26,14 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
 void bootm_announce_and_cleanup(void)
 {
 	printf("\nStarting kernel ...\n\n");
@@ -45,7 +37,6 @@ void bootm_announce_and_cleanup(void)
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
 #endif
-	board_final_cleanup();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index cb45a79857..ceab3cf5e4 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -9,6 +9,37 @@
 #include <asm/coreboot_tables.h>
 #include <asm/e820.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+	/* adjust stack pointer to reserve space for configuration tables */
+	gd->arch.high_table_limit = gd->start_addr_sp;
+	gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+	gd->arch.high_table_ptr = gd->start_addr_sp;
+
+	/* clear the memory */
+	memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+	gd->start_addr_sp &= ~0xf;
+
+	return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+	u32 new_ptr;
+	void *ptr;
+
+	new_ptr = gd->arch.high_table_ptr + bytes;
+	if (new_ptr >= gd->arch.high_table_limit)
+		return NULL;
+	ptr = (void *)gd->arch.high_table_ptr;
+	gd->arch.high_table_ptr = new_ptr;
+
+	return ptr;
+}
+
 /**
  * cb_table_init() - initialize a coreboot table header
  *
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index 3cc6adbbbb..a93d355d8a 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -10,7 +10,6 @@
 #include <pci.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
-#include <asm/tables.h>
 
 static bool irq_already_routed[16];
 
@@ -111,9 +110,6 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
 {
 	struct irq_routing_table *rom_rt;
 
-	/* Fix up the table checksum */
-	rt->checksum = table_compute_checksum(rt, rt->size);
-
 	/* Align the table to be 16 byte aligned */
 	addr = ALIGN(addr, 16);
 
diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c
index 441fca99f1..9f3055020b 100644
--- a/arch/x86/lib/smbios.c
+++ b/arch/x86/lib/smbios.c
@@ -105,8 +105,8 @@ static int smbios_write_type1(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type1));
 	fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 
 	len = t->length + smbios_string_table_len(t->eos);
 	*current += len;
@@ -121,8 +121,8 @@ static int smbios_write_type2(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type2));
 	fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 	t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
 	t->board_type = SMBIOS_BOARD_MOTHERBOARD;
 
@@ -139,7 +139,7 @@ static int smbios_write_type3(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type3));
 	fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
 	t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
 	t->bootup_state = SMBIOS_STATE_SAFE;
 	t->power_supply_state = SMBIOS_STATE_SAFE;
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index a156f2ce31..f92111e4c8 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -80,9 +80,8 @@ void write_tables(void)
 
 #ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
-		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+		high_table = (u32)high_table_malloc(table_size);
 		if (high_table) {
-			memset((void *)high_table, 0, table_size);
 			table_write_funcs[i](high_table);
 
 			cfg_tables[i].start = high_table;
diff --git a/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
index 23b8748c69..b784510f39 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Makefile
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= conga-qeval20-qa3.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 0000000000..eace459ae0
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/bayleybay/.gitignore b/board/intel/bayleybay/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/intel/bayleybay/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile
index 88b5aad634..52dda7ddab 100644
--- a/board/intel/bayleybay/Makefile
+++ b/board/intel/bayleybay/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= bayleybay.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl
new file mode 100644
index 0000000000..21785ea73b
--- /dev/null
+++ b/board/intel/bayleybay/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/intel/bayleybay/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 6515bacd76..87a0ec4ccc 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -21,4 +21,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
 
+config SMBIOS_PRODUCT_NAME
+	default "GalileoGen2"
+	help
+	  Override the default product name U-Boot reports in the SMBIOS
+	  table, to be compatible with the Intel provided UEFI BIOS, as
+	  Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
+	  drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+	  it to do different board level configuration.
+
+	  This can be "Galileo" for GEN1 Galileo board.
+
 endif
diff --git a/board/intel/minnowmax/.gitignore b/board/intel/minnowmax/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/intel/minnowmax/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 1a614324a2..73e5a8fd02 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000000..21785ea73b
--- /dev/null
+++ b/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9336752128..d51645c634 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -593,6 +593,13 @@ config CMD_SOUND
 	     sound init   - set up sound system
 	     sound play   - play a sound
 
+config CMD_QFW
+	bool "qfw"
+	select QFW
+	help
+	  This provides access to the QEMU firmware interface.  The main
+	  feature is to allow easy loading of files passed to qemu-system
+	  via -kernel / -initrd
 endmenu
 
 config CMD_BOOTSTAGE
diff --git a/cmd/Makefile b/cmd/Makefile
index e3e0c74ffc..9ce7861f82 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,6 +105,7 @@ endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
diff --git a/cmd/qfw.c b/cmd/qfw.c
new file mode 100644
index 0000000000..12436ec9b4
--- /dev/null
+++ b/cmd/qfw.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <qfw.h>
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+	char *data_addr;
+	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+	if (setup_size == 0 || kernel_size == 0) {
+		printf("warning: no kernel available\n");
+		return -1;
+	}
+
+	data_addr = load_addr;
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+			      le32_to_cpu(setup_size), data_addr);
+	data_addr += le32_to_cpu(setup_size);
+
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+			      le32_to_cpu(kernel_size), data_addr);
+	data_addr += le32_to_cpu(kernel_size);
+
+	data_addr = initrd_addr;
+	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+	if (initrd_size == 0) {
+		printf("warning: no initrd available\n");
+	} else {
+		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+				      le32_to_cpu(initrd_size), data_addr);
+		data_addr += le32_to_cpu(initrd_size);
+	}
+
+	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+	if (cmdline_size) {
+		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+				      le32_to_cpu(cmdline_size), data_addr);
+		/*
+		 * if kernel cmdline only contains '\0', (e.g. no -append
+		 * when invoking qemu), do not update bootargs
+		 */
+		if (*data_addr != '\0') {
+			if (setenv("bootargs", data_addr) < 0)
+				printf("warning: unable to change bootargs\n");
+		}
+	}
+
+	printf("loading kernel to address %p size %x", load_addr,
+	       le32_to_cpu(kernel_size));
+	if (initrd_size)
+		printf(" initrd %p size %x\n",
+		       initrd_addr,
+		       le32_to_cpu(initrd_size));
+	else
+		printf("\n");
+
+	return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+	int ret;
+	struct fw_cfg_file_iter iter;
+	struct fw_file *file;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret)
+		return ret;
+
+
+	for (file = qemu_fwcfg_file_iter_init(&iter);
+	     !qemu_fwcfg_file_iter_end(&iter);
+	     file = qemu_fwcfg_file_iter_next(&iter)) {
+		printf("%-56s\n", file->cfg.name);
+	}
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (qemu_fwcfg_list_firmware() < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	int ret = qemu_fwcfg_online_cpus();
+	if (ret < 0) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	char *env;
+	void *load_addr;
+	void *initrd_addr;
+
+	env = getenv("loadaddr");
+	load_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_LOADADDR
+		(void *)CONFIG_LOADADDR;
+#else
+		NULL;
+#endif
+
+	env = getenv("ramdiskaddr");
+	initrd_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_RAMDISK_ADDR
+		(void *)CONFIG_RAMDISK_ADDR;
+#else
+		NULL;
+#endif
+
+	if (argc == 2) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	}
+
+	if (!load_addr || !initrd_addr) {
+		printf("missing load or initrd address\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	cmd_tbl_t *fwcfg_cmd;
+
+	if (!qemu_fwcfg_present()) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_USAGE;
+	}
+
+	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+				 ARRAY_SIZE(fwcfg_commands));
+	argc -= 2;
+	argv += 2;
+	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+	return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+	qfw,	4,	1,	do_qemu_fw,
+	"QEMU firmware interface",
+	"<command>\n"
+	"    - list                             : print firmware(s) currently loaded\n"
+	"    - cpus                             : print online cpu number\n"
+	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index ce1f5198ff..9f1d7fbca9 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -9,6 +9,8 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 5186345fde..64fd7c9cff 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -8,6 +8,8 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 7c6b692c6b..8e086c512a 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -8,8 +8,6 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -24,7 +22,6 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 17b14589cc..f8d3c3b8ab 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -4,10 +4,12 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
@@ -30,6 +32,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 9930d56a6b..28b837daab 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,6 +8,8 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 53b1ff65af..45bb3ec0e9 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index aec2e538a1..9e4a92dd6c 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -48,6 +48,7 @@ CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/doc/README.x86 b/doc/README.x86
index c5c3010ee2..4d50feb720 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -23,7 +23,8 @@ In this case, known as bare mode, from the fact that it runs on the
 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
 are supported:
 
-   - Bayley Bay
+   - Bayley Bay CRB
+   - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
    - Galileo
@@ -303,12 +304,12 @@ Offset   Description         Controlling config
 000000   descriptor.bin      Hard-coded to 0 in ifdtool
 001000   me.bin              Set by the descriptor
 500000   <spare>
+6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
 790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
-7fe000   Environment         CONFIG_ENV_OFFSET
 7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
 
 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
@@ -412,18 +413,19 @@ If you want to check both consoles, use '-serial stdio'.
 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
 
-The fw_cfg interface in QEMU also provides information about kernel data, initrd,
-command-line arguments and more. U-Boot supports directly accessing these informtion
-from fw_cfg interface, this saves the time of loading them from hard disk or
-network again, through emulated devices. To use it , simply providing them in
-QEMU command line:
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line:
 
 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
     -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
 
 Note: -initrd and -smp are both optional
 
-Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel:
 
  => qfw
 qfw - QEMU firmware interface
@@ -437,8 +439,8 @@ qfw <command>
 => qfw load
 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
 
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
-can be used to boot the kernel:
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel:
 
 => zboot 02000000 - 04000000 1b1ab50
 
@@ -490,8 +492,8 @@ Booting Ubuntu
 --------------
 As an example of how to set up your boot flow with U-Boot, here are
 instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA driver but are equally applicable on
-other platforms and other media. There are really only four steps and its a
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
 very simple script, but a more detailed explanation is provided here for
 completeness.
 
@@ -499,7 +501,7 @@ Note: It is possible to set up U-Boot to boot automatically using syslinux.
 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
 GUID. If you figure these out, please post patches to this README.
 
-Firstly, you will need Ubunutu installed on an available disk. It should be
+Firstly, you will need Ubuntu installed on an available disk. It should be
 possible to make U-Boot start a USB start-up disk but for now let's assume
 that you used another boot loader to install Ubuntu.
 
@@ -659,7 +661,7 @@ U-Boot:
    Loading bzImage at address 100000 (5805728 bytes)
    Magic signature found
    Initial RAM disk at linear address 0x04000000, size 19215259 bytes
-   Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+   Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
 
    Starting kernel ...
 
@@ -679,13 +681,14 @@ above commands into a script since then it will be faster.
                   240,329  ahci
                 1,422,704  vesa display
 
-Now the kernel actually starts:
+Now the kernel actually starts: (if you want to examine kernel boot up message
+on the serial console, append "console=ttyS0,115200" to the kernel command line)
 
    [    0.000000] Initializing cgroup subsys cpuset
    [    0.000000] Initializing cgroup subsys cpu
    [    0.000000] Initializing cgroup subsys cpuacct
    [    0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
-   [    0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+   [    0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
 
 It continues for a long time. Along the way you will see it pick up your
 ramdisk:
@@ -736,14 +739,6 @@ If you want to put this in a script you can use something like this:
 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
 command.
 
-You will also need to add this to your board configuration file, e.g.
-include/configs/minnowmax.h:
-
-   #define CONFIG_BOOTDELAY	2
-
-Now when you reset your board it wait a few seconds (in case you want to
-interrupt) and then should boot straight into Ubuntu.
-
 You can also bake this behaviour into your build by hard-coding the
 environment variables if you add this to minnowmax.h:
 
@@ -812,6 +807,30 @@ to install/boot a Windows XP OS (below for example command to install Windows).
 This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
 SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
 
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+diff --git a/src/optionroms.c b/src/optionroms.c
+index 65f7fe0..c7b6f5e 100644
+--- a/src/optionroms.c
++++ b/src/optionroms.c
+@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+         rom = deploy_romfile(file);
+     else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+         rom = map_pcirom(pci);
++    if (pci->bdf == pci_to_bdf(0, 2, 0))
++        rom = (struct rom_header *)0xfff90000;
+     if (! rom)
+         // No ROM present.
+         return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
 
 Development Flow
 ----------------
@@ -963,12 +982,62 @@ transformations. Remember to add attribution to coreboot for new files added
 to U-Boot. This should go at the top of each file and list the coreboot
 filename where the code originated.
 
+Debugging ACPI issues with Windows:
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (ACPI) [16] aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from [17] to compile one by yourself.
+
+Current ACPI support in U-Boot is not complete. More features will be added
+in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+   the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+   of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support ACPI interrupts with SCI only.
+
+Features not supported so far (to make it a complete ACPI solution):
+ * S3 (Suspend to RAM), S4 (Suspend to Disk).
+
+Features that are optional:
+ * ACPI global NVS support. We may need it to simplify ASL code logic if
+   utilizing NVS variables. Most likely we will need this sooner or later.
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+   SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+   those legacy stuff into U-Boot. ACPI spec allows a system that does not
+   support SMI (a legacy-free system).
+
+So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
 
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
-- SMI and ACPI support, to provide platform info and facilities to Linux
 
 References
 ----------
@@ -987,3 +1056,5 @@ References
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] http://www.seabios.org/SeaBIOS
 [15] doc/device-tree-bindings/misc/intel,irq-router.txt
+[16] http://www.acpi.info
+[17] https://www.acpica.org/downloads
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index e4d8ead2ee..04ad34654c 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -14,6 +14,11 @@ Required properties :
       "ibase": IRQ routing is in the memory-mapped IBASE register block
 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
     configuration space, required only if intel,pirq-config = "ibase".
+- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
+    be specified. The 8-bit ACTL register is seen on ICH series chipset, like
+    ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
+- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
+    in the interrupt router's PCI configuration space, or IBASE.
 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
     first cell is the register offset that controls the first PIRQ link routing.
     The second cell is the total number of PIRQ links the router supports.
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index af8667f030..c40f6b577f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -138,4 +138,10 @@ config WINBOND_W83627
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QFW
+	bool
+	help
+	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
+	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5969d34444..98704f2085 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_QFW) += qfw.o
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/drivers/misc/qfw.c
index 2e2794ebd7..d43d1d300a 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/drivers/misc/qfw.c
@@ -8,220 +8,20 @@
 #include <command.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/io.h>
-#include <asm/fw_cfg.h>
+#ifdef CONFIG_GENERATE_ACPI_TABLE
 #include <asm/tables.h>
-#include <asm/e820.h>
+#endif
 #include <linux/list.h>
-#include <memalign.h>
 
 static bool fwcfg_present;
 static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
 
 static LIST_HEAD(fw_list);
 
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
-		uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
+#ifdef CONFIG_GENERATE_ACPI_TABLE
 /*
  * This function allocates memory for ACPI tables
  *
@@ -346,41 +146,6 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry)
 	return 0;
 }
 
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
-
 /* This function loads and patches ACPI tables provided by QEMU */
 u32 write_acpi_tables(u32 addr)
 {
@@ -389,7 +154,6 @@ u32 write_acpi_tables(u32 addr)
 	struct bios_linker_entry *table_loader;
 	struct bios_linker_entry *entry;
 	uint32_t size;
-	struct list_head *list;
 
 	/* make sure fw_list is loaded */
 	ret = qemu_fwcfg_read_firmware_list();
@@ -444,10 +208,14 @@ u32 write_acpi_tables(u32 addr)
 
 out:
 	if (ret) {
-		list_for_each(list, &fw_list) {
-			file = list_entry(list, struct fw_file, list);
-			if (file->addr)
+		struct fw_cfg_file_iter iter;
+		for (file = qemu_fwcfg_file_iter_init(&iter);
+		     !qemu_fwcfg_file_iter_end(&iter);
+		     file = qemu_fwcfg_file_iter_next(&iter)) {
+			if (file->addr) {
 				free((void *)file->addr);
+				file->addr = 0;
+			}
 		}
 	}
 
@@ -456,115 +224,163 @@ out:
 }
 #endif
 
-static int qemu_fwcfg_list_firmware(void)
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
 {
-	int ret;
-	struct list_head *entry;
-	struct fw_file *file;
+	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+	      entry, size, address);
 
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
+	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+}
 
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		printf("%-56s\n", file->cfg.name);
-	}
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
 
-	return 0;
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+	      entry, size, address, be32_to_cpu(dma.control));
+
+	fwcfg_arch_ops->arch_read_dma(&dma);
 }
 
-void qemu_fwcfg_init(void)
+bool qemu_fwcfg_present(void)
 {
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
+	return fwcfg_present;
 }
 
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+bool qemu_fwcfg_dma_present(void)
 {
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
+	return fwcfg_dma_present;
+}
 
-	return 0;
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
 }
 
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+int qemu_fwcfg_online_cpus(void)
 {
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
+	uint16_t nb_cpus;
 
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+	if (!fwcfg_present)
+		return -ENODEV;
 
-	return 0;
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
 }
 
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+int qemu_fwcfg_read_firmware_list(void)
 {
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
 	}
 
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
+	return 0;
 
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
 
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+struct fw_file *qemu_fwcfg_find_file(const char *name)
 {
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
+	struct list_head *entry;
+	struct fw_file *file;
 
-	if (!fwcfg_present) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
 	}
 
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
+	return NULL;
+}
 
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = ((struct list_head *)iter->entry)->next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
 
-	return cmd_process_error(fwcfg_cmd, ret);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
 }
 
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
+{
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+	fwcfg_arch_ops = NULL;
+
+	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+		return;
+	fwcfg_arch_ops = ops;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
+}
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 674d1f602b..95ad1287f6 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -40,6 +40,6 @@
 #define CONFIG_X86EMU_RAW_IO
 
 #define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_OFFSET		0x007fe000
+#define CONFIG_ENV_OFFSET		0x006ef000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index b79f47baf3..b4aad6cd24 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -193,14 +193,19 @@
 #define CONFIG_HOSTNAME		x86
 #define CONFIG_BOOTFILE		"bzImage"
 #define CONFIG_LOADADDR		0x1000000
-#define CONFIG_RAMDISK_ADDR		0x4000000
+#define CONFIG_RAMDISK_ADDR	0x4000000
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#define CONFIG_OTHBOOTARGS	"othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	CONFIG_STD_DEVICES_SETTINGS			\
 	"pciconfighost=1\0"				\
 	"netdev=eth0\0"					\
 	"consoledev=ttyS0\0"				\
-	"othbootargs=acpi=off\0"			\
+	CONFIG_OTHBOOTARGS				\
 	"ramdiskaddr=0x4000000\0"			\
 	"ramdiskfile=initramfs.gz\0"
 
diff --git a/arch/x86/include/asm/fw_cfg.h b/include/qfw.h
index e9450c6196..b0b3b5945e 100644
--- a/arch/x86/include/asm/fw_cfg.h
+++ b/include/qfw.h
@@ -7,11 +7,6 @@
 #ifndef __FW_CFG__
 #define __FW_CFG__
 
-#define FW_CONTROL_PORT	0x510
-#define FW_DATA_PORT		0x511
-#define FW_DMA_PORT_LOW	0x514
-#define FW_DMA_PORT_HIGH	0x518
-
 #include <linux/list.h>
 
 enum qemu_fwcfg_items {
@@ -87,12 +82,22 @@ struct fw_file {
 	struct list_head list;  /* list node to link to fw_list */
 };
 
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
 struct fw_cfg_dma_access {
 	__be32 control;
 	__be32 length;
 	__be64 address;
 };
 
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
 struct bios_linker_entry {
 	__le32 command;
 	union {
@@ -144,8 +149,14 @@ struct bios_linker_entry {
 
 /**
  * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
  */
-void qemu_fwcfg_init(void);
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
 
 /**
  * Get system cpu number
@@ -154,4 +165,12 @@ void qemu_fwcfg_init(void);
  */
 int qemu_fwcfg_online_cpus(void);
 
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
 #endif
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ad1d9b5d7d..97a09a272c 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -323,13 +323,13 @@ $(obj)/%.S: $(src)/%.ttf
 
 # ACPI
 # ---------------------------------------------------------------------------
-quiet_cmd_acpi_c_asl= ASL     $@
+quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
-	iasl -p $< -tc -va $<.tmp; \
+	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-$(obj)/%.c:    $(src)/%.asl
+$(obj)/dsdt.c:    $(src)/dsdt.asl
 	$(call cmd,acpi_c_asl)
 
 # Bzip2