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authorTom Rini <trini@konsulko.com>2022-03-30 18:07:23 -0400
committerTom Rini <trini@konsulko.com>2022-04-08 10:46:22 -0400
commit55b3ba4c2ba4c464491604c5da63debae72aa5c6 (patch)
treed9c1f95b2ba4e6b44b917431a764afcced7fe72b
parent5d14c336b21da34d07e93b5689ccffd52b8cc658 (diff)
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spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat
-rw-r--r--arch/arm/mach-socfpga/misc_soc64.c1
-rw-r--r--configs/j7200_evm_a72_defconfig2
-rw-r--r--configs/j7200_evm_r5_defconfig2
-rw-r--r--configs/j721e_evm_a72_defconfig2
-rw-r--r--configs/j721e_evm_r5_defconfig2
-rw-r--r--configs/j721e_hs_evm_a72_defconfig2
-rw-r--r--configs/j721e_hs_evm_r5_defconfig2
-rw-r--r--configs/j721s2_evm_a72_defconfig2
-rw-r--r--configs/j721s2_evm_r5_defconfig2
-rw-r--r--configs/k2g_evm_defconfig2
-rw-r--r--configs/k2g_hs_evm_defconfig2
-rw-r--r--configs/stv0991_defconfig2
-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/cadence_qspi.c4
-rw-r--r--drivers/spi/cadence_qspi.h1
-rw-r--r--include/configs/j721e_evm.h1
-rw-r--r--include/configs/j721s2_evm.h1
-rw-r--r--include/configs/k2g_evm.h4
-rw-r--r--include/configs/socfpga_common.h9
-rw-r--r--include/configs/socfpga_soc64_common.h5
-rw-r--r--include/configs/stv0991.h8
21 files changed, 35 insertions, 29 deletions
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 7b973a79e8..2acdfad07b 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -16,6 +16,7 @@
#include <errno.h>
#include <init.h>
#include <log.h>
+#include <mach/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index eb1d7d46b8..3d0d1977ff 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index e500a27bb6..0f4b006b80 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -134,6 +134,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 447967add2..792a9021d7 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -173,6 +173,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index e6a5f99505..6553212de8 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -127,6 +127,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index b468a4438e..8146af9732 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -145,6 +145,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
index 1e4a93ff53..aaf3c2b5b0 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -114,6 +114,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 7e2bbc482d..e0d124575c 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -181,6 +181,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 996efd4db2..4147b4e26c 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -138,6 +138,8 @@ CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 440a76f443..251a982492 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -89,6 +89,8 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 4137733c0f..d89eb41b6b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -73,6 +73,8 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=384000000
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index e8d8509608..d58d6c3c9c 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -39,3 +39,5 @@ CONFIG_PHY_RESET_DELAY=10000
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=3000000
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 423a757141..8dba95ae4e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -128,6 +128,14 @@ config CADENCE_QSPI
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+config HAS_CQSPI_REF_CLK
+ bool "Cadence QSPI static reference clock"
+ depends on CADENCE_QSPI
+
+config CQSPI_REF_CLK
+ int "Cadence QSPI reference clock value in Hz"
+ depends on HAS_CQSPI_REF_CLK
+
config CF_SPI
bool "ColdFire SPI driver"
help
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index db680618ee..7209bb43a7 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -188,8 +188,10 @@ static int cadence_spi_probe(struct udevice *bus)
if (plat->ref_clk_hz == 0) {
ret = clk_get_by_index(bus, 0, &clk);
if (ret) {
-#ifdef CONFIG_CQSPI_REF_CLK
+#ifdef CONFIG_HAS_CQSPI_REF_CLK
plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#elif defined(CONFIG_ARCH_SOCFPGA)
+ plat->ref_clk_hz = cm_get_qspi_controller_clk_hz();
#else
return ret;
#endif
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 19345cac5a..a2b620a5fe 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -95,5 +95,6 @@ void cadence_qspi_apb_delay(void *reg_base,
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
void cadence_qspi_apb_readdata_capture(void *reg_base,
unsigned int bypass, unsigned int delay);
+unsigned int cm_get_qspi_controller_clk_hz(void);
#endif /* __CADENCE_QSPI_H__ */
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 5aaa31eaa1..df3c16540b 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -57,7 +57,6 @@
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONFIG_CQSPI_REF_CLK 133333333
/* HyperFlash related configuration */
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 8788464923..f0d56b8778 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -58,7 +58,6 @@
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONFIG_CQSPI_REF_CLK 133333333
/* U-Boot general configuration */
#define EXTRA_ENV_J721S2_BOARD_SETTINGS \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 294ce4662e..887fda90d6 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -59,10 +59,6 @@
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CQSPI_REF_CLK 384000000
-#endif
-
#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS
#include <configs/ti_armv7_keystone2.h>
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index e094bef3b5..5ecd1e6399 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -122,15 +122,6 @@
#endif
/*
- * QSPI support
- */
-/* QSPI reference clock */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
-#endif
-
-/*
* USB
*/
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index b810567a03..c288d548f5 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -61,11 +61,6 @@
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif /* CONFIG_SPL_BUILD */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
-#endif
-
#endif /* CONFIG_CADENCE_QSPI */
/*
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index feec8695f2..137672909b 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -31,12 +31,4 @@
/* Misc configuration */
-/*
-+ * QSPI support
-+ */
-#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
-
-#endif
-
#endif /* __CONFIG_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:32:38 +0000