mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode

The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

5 files changed, 30 insertions, 46 deletions

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index eb256e598d..3ac91619c4 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,53 @@ void cpu_init_f (volatile immap_t * im)
 
 #ifdef CFG_ACR_PIPE_DEP
 	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
 #endif
 
 #ifdef CFG_SPCR_TSEC1EP
 	/* TSEC1 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
 #endif
 
 #ifdef CFG_SPCR_TSEC2EP
 	/* TSEC2 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
 #endif
 
+#ifdef CONFIG_MPC834X
 #ifdef CFG_SCCR_TSEC1CM
 	/* TSEC1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
 #endif
 #ifdef CFG_SCCR_TSEC2CM
 	/* TSEC2 & I2C1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_USBMPHCM
+	/* USB MPH clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#endif
+#endif /* CONFIG_MPC834X */
+
+#ifdef CFG_SCCR_PCICM
+	/* PCI & DMA clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_USBDRCM
+	/* USB DR clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_ENCCM
+	/* Encryption clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
 #endif
 
 #ifdef CFG_ACR_RPTCNT
 	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
 #endif
 
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index a6d82b98f3..0460be9e56 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -60,17 +60,6 @@
 #endif
 #endif
 
-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
 #define CFG_IMMR		0xE0000000
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 728083b304..ed0357791b 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -57,17 +57,6 @@
  */
 #define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
 
-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 62606b302d..65aac5cefd 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -63,17 +63,6 @@
 #endif
 #endif
 
-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
 #undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
 #define CFG_IMMR		0xE0000000
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 33f02ef07d..c2a4ff5877 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -509,6 +509,7 @@
 #define SCCR_PCICM_SHIFT		16
 
 /* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -522,6 +523,7 @@
 #define SCCR_TSEC2CM_1			0x10000000
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
+#endif
 
 #define SCCR_USBMPHCM			0x00c00000
 #define SCCR_USBMPHCM_SHIFT		22
@@ -533,13 +535,6 @@
 #define SCCR_USBCM_2			0x00A00000
 #define SCCR_USBCM_3			0x00F00000
 
-#define SCCR_CLK_MASK			( SCCR_TSEC1CM_3	\
-					| SCCR_TSEC2CM_3	\
-					| SCCR_ENCCM_3		\
-					| SCCR_USBCM_3		)
-
-#define SCCR_DEFAULT			0xFFFFFFFF
-
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
 #define CSBNDS_SA			0x00FF0000