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author | Tom Rini <trini@konsulko.com> | 2024-09-10 07:50:05 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-09-10 07:50:05 -0600 |
commit | 40727391702a1a48c58b0a3c6e69013ff8af6cb2 (patch) | |
tree | 84b20693c9f3dd5d5cc831d0b999bd5523523c35 | |
parent | aded8e4aaee1efa32f2ce7e3c45205f523afc2da (diff) | |
parent | 1806fed0ce6b56365ecf6b84ce6d17aafd3af979 (diff) | |
download | u-boot-40727391702a1a48c58b0a3c6e69013ff8af6cb2.tar.gz u-boot-40727391702a1a48c58b0a3c6e69013ff8af6cb2.tar.bz2 u-boot-40727391702a1a48c58b0a3c6e69013ff8af6cb2.zip |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292
- Add rdcycle to RISC-V exception command
- Some fixes and refactoring
-rw-r--r-- | arch/riscv/Kconfig | 14 | ||||
-rw-r--r-- | arch/riscv/include/asm/bitops.h | 40 | ||||
-rw-r--r-- | arch/riscv/lib/interrupts.c | 7 | ||||
-rw-r--r-- | board/starfive/visionfive2/spl.c | 15 | ||||
-rw-r--r-- | cmd/riscv/exception.c | 15 | ||||
-rw-r--r-- | drivers/clk/analogbits/wrpll-cln28hpc.c | 6 | ||||
-rw-r--r-- | drivers/clk/sifive/fu540-prci.c | 7 | ||||
-rw-r--r-- | drivers/clk/sifive/fu540-prci.h | 22 | ||||
-rw-r--r-- | drivers/clk/sifive/fu740-prci.c | 7 | ||||
-rw-r--r-- | drivers/clk/sifive/fu740-prci.h | 22 | ||||
-rw-r--r-- | drivers/clk/sifive/sifive-prci.c | 3 | ||||
-rw-r--r-- | drivers/clk/sifive/sifive-prci.h | 4 |
12 files changed, 102 insertions, 60 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52..876bec35bc 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -133,6 +133,7 @@ config FRAMEPOINTER config SPL_FRAMEPOINTER bool "Build SPL with frame pointer for stack unwinding" + depends on SPL help Choose this option to use the frame pointer so the stack can be unwound if needed. This is useful for tracing where faults came @@ -437,7 +438,20 @@ config AVAILABLE_HARTS If disable this, it will send IPI by CPUs node numbers of device tree. config SHOW_REGS + default y bool "Show registers on unhandled exception" + help + By default only the program counter and the return address register + are shown in crash dumps. Enable this symbol to show all registers in + main U-Boot. + +config SPL_SHOW_REGS + bool "In SPL show registers on unhandled exception" + depends on SPL + help + By default only the program counter and the return address register + are shown in crash dumps. Enable this symbol to show all registers in + SPL. config RISCV_PRIV_1_9 bool "Use version 1.9 of the RISC-V priviledged specification" diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 35f1368b83..2f2994c4dd 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -138,6 +138,43 @@ static inline unsigned long ffz(unsigned long word) return k; } +static inline int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG); + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= (BITS_PER_LONG - 1); + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if (~tmp) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore @@ -158,6 +195,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + #define test_and_set_bit __test_and_set_bit #define test_and_clear_bit __test_and_clear_bit diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index f9a1428a48..714cc92d03 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -34,9 +34,8 @@ static void show_efi_loaded_images(uintptr_t epc) efi_print_image_infos((void *)epc); } -static void show_regs(struct pt_regs *regs) +static void __maybe_unused show_regs(struct pt_regs *regs) { -#ifdef CONFIG_SHOW_REGS printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", regs->sp, regs->gp, regs->tp); printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n", @@ -57,7 +56,6 @@ static void show_regs(struct pt_regs *regs) regs->s10, regs->s11, regs->t3); printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n", regs->t4, regs->t5, regs->t6); -#endif } static void __maybe_unused show_backtrace(struct pt_regs *regs) @@ -157,7 +155,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); - show_regs(regs); + if (CONFIG_IS_ENABLED(SHOW_REGS)) + show_regs(regs); if (CONFIG_IS_ENABLED(FRAMEPOINTER)) show_backtrace(regs); show_code(epc); diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index b794b73b6b..f55c6b5d34 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -170,23 +170,32 @@ void spl_fdt_fixup_mars_cm(void *fdt) { const char *compat; const char *model; + int compat_size; spl_fdt_fixup_mars(fdt); if (!get_mmc_size_from_eeprom()) { int offset; + static const char + compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110"; model = "Milk-V Mars CM Lite"; - compat = "milkv,mars-cm-lite\0starfive,jh7110"; + compat = compat_cm_lite; + compat_size = sizeof(compat_cm_lite); offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); } else { + static const char + compat_cm[] = "milkv,mars-cm\0starfive,jh7110"; + model = "Milk-V Mars CM"; - compat = "milkv,mars-cm\0starfive,jh7110"; + compat = compat_cm; + compat_size = sizeof(compat_cm); } - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), + "compatible", compat, compat_size); fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); } diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 2b58b1c449..16e335327f 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -36,6 +36,14 @@ static int do_ialign16(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } +static int do_rdcycle(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + printf("cycle = 0x%lx\n", csr_read(CSR_CYCLE)); + + return CMD_RET_SUCCESS; +} + static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -62,6 +70,8 @@ static struct cmd_tbl cmd_sub[] = { "", ""), U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16, "", ""), + U_BOOT_CMD_MKENT(rdcycle, CONFIG_SYS_MAXARGS, 1, do_rdcycle, + "", ""), U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, "", ""), U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, @@ -74,7 +84,8 @@ U_BOOT_LONGHELP(exception, " compressed - compressed instruction\n" " ebreak - breakpoint\n" " ialign16 - 16 bit aligned instruction\n" - " undefined - illegal instruction\n" - " unaligned - load address misaligned\n"); + " rdcycle - read cycle CSR\n" + " unaligned - load address misaligned\n" + " undefined - illegal instruction\n"); #include <exception.h> diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index a3cb109d35..537c696b72 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -81,7 +81,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq) { if (post_divr_freq < MIN_POST_DIVR_FREQ || post_divr_freq > MAX_POST_DIVR_FREQ) { - WARN(1, "%s: post-divider reference freq out of range: %lu", + WARN(1, "%s: post-divider reference freq out of range: %lu\n", __func__, post_divr_freq); return -ERANGE; } @@ -229,7 +229,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, int range; if (c->flags == 0) { - WARN(1, "%s called with uninitialized PLL config", __func__); + WARN(1, "%s called with uninitialized PLL config\n", __func__); return -EINVAL; } @@ -335,7 +335,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, u64 n; if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { - WARN(1, "external feedback mode not yet supported"); + WARN(1, "external feedback mode not yet supported\n"); return ULONG_MAX; } diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0..e55a26ab8f 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { +static struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; + +const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h deleted file mode 100644 index 113301107d..0000000000 --- a/drivers/clk/sifive/fu540-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU540_PRCI_H -#define __SIFIVE_CLK_FU540_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU540 4 - -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; - -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - -#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 5edc864e4b..4274b215d2 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { +static struct __prci_clock __prci_init_clocks_fu740[] = { [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .pwd = &__prci_pcieaux_data, } }; + +const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h deleted file mode 100644 index b74f078906..0000000000 --- a/drivers/clk/sifive/fu740-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU740_PRCI_H -#define __SIFIVE_CLK_FU740_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU740 9 - -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; - -static const struct prci_clk_desc prci_clk_fu740 = { - .clks = __prci_init_clocks_fu740, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), -}; - -#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 5ea8606280..aa26d3a109 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -33,8 +33,7 @@ #include <linux/math64.h> #include <dt-bindings/clock/sifive-fu740-prci.h> -#include "fu540-prci.h" -#include "fu740-prci.h" +#include "sifive-prci.h" /* * Private functions diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 5ce33d6184..b391698081 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); +/* Clock driver data */ +extern const struct prci_clk_desc prci_clk_fu540; +extern const struct prci_clk_desc prci_clk_fu740; + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ |