powerpc: kvme080: remove orphan board

This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>

7 files changed, 1 insertions, 801 deletions

diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile
deleted file mode 100644
index d1b6f30440..0000000000
--- a/board/etin/kvme080/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= kvme080.o multiverse.o
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
deleted file mode 100644
index baf4cbc4da..0000000000
--- a/board/etin/kvme080/kvme080.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-int checkboard(void)
-{
-	puts ("Board: KVME080\n");
-	return 0;
-}
-
-unsigned long setdram(int m, int row, int col, int bank)
-{
-	int i;
-	unsigned long start, end;
-	uint32_t mccr1;
-	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
-	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
-	uint8_t mber = 0;
-
-	CONFIG_READ_WORD(MCCR1, mccr1);
-	mccr1 &= 0xffff0000;
-
-	start = CONFIG_SYS_SDRAM_BASE;
-	end = start + (1 << (col + row + 3) ) * bank - 1;
-
-	for (i = 0; i < m; i++) {
-		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
-		if (i < 4) {
-			msar1  |= ((start >> 20) & 0xff) << i * 8;
-			emsar1 |= ((start >> 28) & 0xff) << i * 8;
-			mear1  |= ((end >> 20) & 0xff) << i * 8;
-			emear1 |= ((end >> 28) & 0xff) << i * 8;
-		} else {
-			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
-			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
-			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
-			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
-		}
-		mber |= 1 << i;
-		start += (1 << (col + row + 3) ) * bank;
-		end += (1 << (col + row + 3) ) * bank;
-	}
-	for (; i < 8; i++) {
-		if (i < 4) {
-			msar1  |= 0xff << i * 8;
-			emsar1 |= 0x30 << i * 8;
-			mear1  |= 0xff << i * 8;
-			emear1 |= 0x30 << i * 8;
-		} else {
-			msar2  |= 0xff << (i-4) * 8;
-			emsar2 |= 0x30 << (i-4) * 8;
-			mear2  |= 0xff << (i-4) * 8;
-			emear2 |= 0x30 << (i-4) * 8;
-		}
-	}
-
-	CONFIG_WRITE_WORD(MCCR1, mccr1);
-	CONFIG_WRITE_WORD(MSAR1, msar1);
-	CONFIG_WRITE_WORD(EMSAR1, emsar1);
-	CONFIG_WRITE_WORD(MEAR1, mear1);
-	CONFIG_WRITE_WORD(EMEAR1, emear1);
-	CONFIG_WRITE_WORD(MSAR2, msar2);
-	CONFIG_WRITE_WORD(EMSAR2, emsar2);
-	CONFIG_WRITE_WORD(MEAR2, mear2);
-	CONFIG_WRITE_WORD(EMEAR2, emear2);
-	CONFIG_WRITE_BYTE(MBER, mber);
-
-	return (1 << (col + row + 3) ) * bank * m;
-}
-
-phys_size_t initdram(int board_type)
-{
-	unsigned int msr;
-	long int size = 0;
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
-	mtmsr(msr);
-
-	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
-		size = 0x20000000;	/* 512MB */
-	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
-		size = 0x04000000;	/* 64MB */
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
-	mtmsr(msr);
-
-	return size;
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-int board_early_init_f(void)
-{
-	*(volatile unsigned char *)(0xff080120) = 0xfb;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	unsigned int msr;
-
-	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
-	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
-	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtmsr(msr);
-
-	return 0;
-}
-
-extern int multiverse_init(void);
-
-int misc_init_r(void)
-{
-	multiverse_init();
-	return 0;
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*) dest;
-	volatile uchar *s = (volatile uchar*) src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-	return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*)dest;
-	volatile uchar *s = (volatile uchar*)src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c
deleted file mode 100644
index 2bcfe2ea04..0000000000
--- a/board/etin/kvme080/multiverse.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * multiverse.c
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/compiler.h>
-
-#include "multiverse.h"
-
-static unsigned long vme_asi_addr;
-static unsigned long vme_iack_addr;
-static unsigned long pci_reg_addr;
-static unsigned long vme_reg_addr;
-
-int multiv_reset(unsigned long base)
-{
-	writeb(0x09, base + VME_SLAVE32_AM);
-	writeb(0x39, base + VME_SLAVE24_AM);
-	writeb(0x29, base + VME_SLAVE16_AM);
-	writeb(0x2f, base + VME_SLAVE_REG_AM);
-	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
-	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
-	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
-#ifdef A32_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
-				base + VME_SLAVE32_MASK);
-		writeb(0x01, base + VME_SLAVE32_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE32_MASK);
-		writeb(0x00, base + VME_SLAVE32_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE32_MASK);
-	writeb(0x00, base + VME_SLAVE32_EN);
-#endif
-#ifdef A24_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE24_MASK);
-		writeb(0x01, base + VME_SLAVE24_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE24_MASK);
-		writeb(0x00, base + VME_SLAVE24_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE24_MASK);
-	writeb(0x00, base + VME_SLAVE24_EN);
-#endif
-#ifdef A16_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
-				base + VME_SLAVE16_MASK);
-		writeb(0x01, base + VME_SLAVE16_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE16_MASK);
-		writeb(0x00, base + VME_SLAVE16_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE16_MASK);
-	writeb(0x00, base + VME_SLAVE16_EN);
-#endif
-#ifdef REG_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE_REG_MASK);
-		writeb(0x01, base + VME_SLAVE_REG_EN);
-	} else {
-		writeb(0xf8, base + VME_SLAVE_REG_MASK);
-	}
-#else
-	writeb(0xf8, base + VME_SLAVE_REG_MASK);
-#endif
-	writeb(0x09, base + VME_MASTER32_AM);
-	writeb(0x39, base + VME_MASTER24_AM);
-	writeb(0x29, base + VME_MASTER16_AM);
-	writeb(0x2f, base + VME_MASTER_REG_AM);
-	writel(0x00000000, base + VME_RMW_ADRS);
-	writeb(0x00, base + VME_IRQ);
-	writeb(0x00, base + VME_INT_EN);
-	writel(0x00000000, base + VME_IRQ1_REG);
-	writel(0x00000000, base + VME_IRQ2_REG);
-	writel(0x00000000, base + VME_IRQ3_REG);
-	writel(0x00000000, base + VME_IRQ4_REG);
-	writel(0x00000000, base + VME_IRQ5_REG);
-	writel(0x00000000, base + VME_IRQ6_REG);
-	writel(0x00000000, base + VME_IRQ7_REG);
-	return 0;
-}
-
-void multiv_auto_slot_id(unsigned long base)
-{
-	__maybe_unused unsigned int vector;
-	int slot_id = 1;
-	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
-		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
-		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
-		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
-				base + VME_CTRL);
-		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
-		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-			while (readb(base + VME_INT) & 0x04) {
-				vector = *(volatile unsigned int*)
-					(vme_iack_addr + VME_IACK2);
-				*(unsigned char*)(vme_asi_addr + 0x7ffff)
-					= (slot_id << 3) & 0xff;
-				slot_id ++;
-				if (slot_id > 31)
-					break;
-			}
-		}
-	}
-}
-
-int multiverse_init(void)
-{
-	int i;
-	pci_dev_t pdev;
-	unsigned int bar[6];
-
-	pdev = pci_find_device(0x1895, 0x0001, 0);
-
-	if (pdev == 0)
-		return -1;
-
-	for (i = 0; i < 6; i++)
-		pci_read_config_dword (pdev,
-				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
-
-	pci_reg_addr = bar[0];
-	vme_reg_addr = bar[1] + 0x00F00000;
-	vme_iack_addr = bar[1] + 0x00200000;
-	vme_asi_addr = bar[3];
-
-	pci_write_config_dword (pdev, PCI_COMMAND,
-		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-	writel(0xFF000000, pci_reg_addr + P_TA1);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
-	writel(0xf0000000, pci_reg_addr + P_TA2);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
-	writel(0xF1000000, pci_reg_addr + P_TA3);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
-	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
-	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
-
-	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
-	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
-	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
-
-	writel(0xF0000000, pci_reg_addr + W_BA2);
-	writel(0xFF000000, pci_reg_addr + W_AM2);
-	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
-
-	writel(0xFF000000, pci_reg_addr + W_BA3);
-	writel(0xFF000000, pci_reg_addr + W_AM3);
-	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
-
-	writel(0x00000001, pci_reg_addr + W_ERR_CS);
-	writel(0x00000001, pci_reg_addr + P_ERR_CS);
-
-	multiv_reset(vme_reg_addr);
-	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
-		vme_reg_addr + VME_CTRL);
-
-	multiv_auto_slot_id(vme_reg_addr);
-
-	return 0;
-}
diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h
deleted file mode 100644
index b3b79b7ee3..0000000000
--- a/board/etin/kvme080/multiverse.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * multiverse.h
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MULTIVERSE_H__
-#define __MULTIVERSE_H__
-
-#define VME_A32_MSTR_BUS	0x90000000
-#define VME_A32_MSTR_SIZE	0x01000000
-
-#define VME_A32_SLV_SIZE	0x01000000
-
-#define VME_A32_SLV_BUS		0x90000000
-#define VME_A24_SLV_BUS		0x00000000
-#define VME_A16_SLV_BUS		0x00000000
-
-#define VME_A32_SLV_LOCAL	0x00000000
-#define VME_A24_SLV_LOCAL	0x00000000
-#define VME_A16_SLV_LOCAL	0x00000000
-
-#define A32_SLV_WINDOW
-#undef	A24_SLV_WINDOW
-#undef	A16_SLV_WINDOW
-#undef	REG_SLV_WINDOW
-
-/* PCI Registers */
-
-#define P_IMG_CTRL0		0x100
-#define P_BA0			0x104
-#define P_AM0			0x108
-#define P_TA0			0x10C
-#define P_IMG_CTRL1		0x110
-#define P_BA1			0x114
-#define P_AM1			0x118
-#define P_TA1			0x11C
-#define P_IMG_CTRL2		0x120
-#define P_BA2			0x124
-#define P_AM2			0x128
-#define P_TA2			0x12C
-#define P_IMG_CTRL3		0x130
-#define P_BA3			0x134
-#define P_AM3			0x138
-#define P_TA3			0x13C
-#define P_IMG_CTRL4		0x140
-#define P_BA4			0x144
-#define P_AM4			0x148
-#define P_TA4			0x14C
-#define P_IMG_CTRL5		0x150
-#define P_BA5			0x154
-#define P_AM5			0x158
-#define P_TA5			0x15C
-#define P_ERR_CS		0x160
-#define P_ERR_ADDR		0x164
-#define P_ERR_DATA		0x168
-
-#define WB_CONF_SPC_BAR		0x180
-#define W_IMG_CTRL1		0x184
-#define W_BA1			0x188
-#define W_AM1			0x18C
-#define W_TA1			0x190
-#define W_IMG_CTRL2		0x194
-#define W_BA2			0x198
-#define W_AM2			0x19C
-#define W_TA2			0x1A0
-#define W_IMG_CTRL3		0x1A4
-#define W_BA3			0x1A8
-#define W_AM3			0x1AC
-#define W_TA3			0x1B0
-#define W_IMG_CTRL4		0x1B4
-#define W_BA4			0x1B8
-#define W_AM4			0x1BC
-#define W_TA4			0x1C0
-#define W_IMG_CTRL5		0x1C4
-#define W_BA5			0x1C8
-#define W_AM5			0x1CC
-#define W_TA5			0x1D0
-#define W_ERR_CS		0x1D4
-#define W_ERR_ADDR		0x1D8
-#define W_ERR_DATA		0x1DC
-#define CNF_ADDR		0x1E0
-#define CNF_DATA		0x1E4
-#define INT_ACK			0x1E8
-#define ICR			0x1EC
-#define ISR			0x1F0
-
-/* VME registers */
-
-#define VME_SLAVE32_AM		0x03
-#define VME_SLAVE24_AM		0x02
-#define VME_SLAVE16_AM		0x01
-#define VME_SLAVE_REG_AM	0x00
-#define VME_SLAVE32_A		0x07
-#define VME_SLAVE24_A		0x06
-#define VME_SLAVE16_A		0x05
-#define VME_SLAVE_REG_A		0x04
-#define VME_SLAVE32_MASK	0x0B
-#define VME_SLAVE24_MASK	0x0A
-#define VME_SLAVE16_MASK	0x09
-#define VME_SLAVE_REG_MASK	0x08
-#define VME_SLAVE32_EN		0x0F
-#define VME_SLAVE24_EN		0x0E
-#define VME_SLAVE16_EN		0x0D
-#define VME_SLAVE_REG_EN	0x0C
-#define VME_MASTER32_AM		0x13
-#define VME_MASTER24_AM		0x12
-#define VME_MASTER16_AM		0x11
-#define VME_MASTER_REG_AM	0x10
-#define VME_RMW_ADRS		0x14
-#define VME_MBOX		0x18
-#define VME_STATUS		0x1E
-#define VME_CTRL		0x1C
-#define VME_IRQ			0x20
-#define VME_INT_EN		0x21
-#define VME_INT			0x22
-#define VME_IRQ1_REG		0x24
-#define VME_IRQ2_REG		0x28
-#define VME_IRQ3_REG		0x2C
-#define VME_IRQ4_REG		0x30
-#define VME_IRQ5_REG		0x34
-#define VME_IRQ6_REG		0x38
-#define VME_IRQ7_REG		0x3C
-
-/* VME control register */
-
-#define VME_CTRL_BRDRST		0x01
-#define VME_CTRL_SYSRST		0x02
-#define VME_CTRL_RMW		0x04
-#define VME_CTRL_SHORT_D	0x08
-#define VME_CTRL_SYSFAIL	0x10
-#define VME_CTRL_VOWN		0x20
-#define VME_CTRL_A16_REG_MODE	0x40
-
-/* VME status register */
-
-#define VME_STATUS_SYSCON	0x01
-#define VME_STATUS_SYSFAIL	0x02
-#define VME_STATUS_ACFAIL	0x04
-#define VME_STATUS_SYSRST	0x08
-#define VME_STATUS_VOWN		0x10
-
-/* Interrupt types */
-
-#define LVL1			0x0002
-#define LVL2			0x0004
-#define LVL3			0x0008
-#define LVL4			0x0010
-#define LVL5			0x0020
-#define LVL6			0x0040
-#define LVL7			0x0080
-#define MULTIVERSE_INTI_INT	0x0100
-#define MULTIVERSE_WB_INT	0x0200
-#define MULTIVERSE_PCI_INT	0x0400
-
-/* interrupt acknowledge */
-
-#define VME_IACK1		0x04
-#define VME_IACK2		0x08
-#define VME_IACK3		0x0c
-#define VME_IACK4		0x10
-#define VME_IACK5		0x14
-#define VME_IACK6		0x18
-#define VME_IACK7		0x1c
-
-#endif /* __MULTIVERSE_H__ */
diff --git a/boards.cfg b/boards.cfg
index d6810d6a1a..52b7a48d01 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1241,7 +1241,6 @@ Orphan  powerpc     mpc5xxx        -           matrix_vision   mvbc_p
 Orphan  powerpc     mpc5xxx        -           matrix_vision   mvsmr               MVSMR                                 -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
 Orphan  powerpc     mpc824x        -           -               hidden_dragon       HIDDEN_DRAGON                         -                                                                                                                                 Yusdi Santoso <yusdi_santoso@adaptec.com>
 Orphan  powerpc     mpc824x        -           etin            -                   debris                                -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
-Orphan  powerpc     mpc824x        -           etin            -                   kvme080                               -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                           -                                                                                                                                 Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                        MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                             -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 2b9eb69a9d..a8312de66b 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+kvme080          powerpc     mpc824x        -           -           Sangmoon Kim <dogoil@etinsys.com>
 ep8248           powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 ispan            powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 rattler          powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
deleted file mode 100644
index c352a1c804..0000000000
--- a/include/configs/kvme080.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC8245		1
-#define CONFIG_KVME080		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_IPADDR		192.168.0.2
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_SERVERIP		192.168.0.1
-
-#define CONFIG_BOOTARGS \
-	"console=ttyS0,115200 " \
-	"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
-	"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
-	"kvme080:eth0:none " \
-	"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
-
-#define CONFIG_BOOTCOMMAND \
-	"tftp 800000 kvme080/uImage; " \
-	"bootm 800000"
-
-#define CONFIG_LOADADDR		800000
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_LOADS_ECHO	1
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#undef	CONFIG_WATCHDOG
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_DS164x
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		256
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000
-#define CONFIG_SYS_MEMTEST_END		0x07C00000
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x7C000000
-#define CONFIG_SYS_EUMB_ADDR		0xFC000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFF000000
-#define CONFIG_SYS_NS16550_COM1	0xFF080000
-#define CONFIG_SYS_NS16550_COM2	0xFF080010
-#define CONFIG_SYS_NS16550_COM3	0xFF080020
-#define CONFIG_SYS_NS16550_COM4	0xFF080030
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
-#define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
-#define CONFIG_SYS_NVRAM_SIZE		0x7FFF8
-
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_MONITOR_LEN		0x00040000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_PROTECT_CLEAR
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK	0
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-
-#define CONFIG_ENV_IS_IN_NVRAM	1
-#define CONFIG_ENV_OVERWRITE	1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
-#define CONFIG_ENV_SIZE		0x400
-#define CONFIG_ENV_OFFSET		0
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		14745600
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-
-#define CONFIG_EEPRO100
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define CONFIG_SYS_RX_ETH_BUFFER	8
-
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED		400000
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define CONFIG_SYS_CLK_FREQ	33333333
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_SYS_DLL_EXTEND		0x00
-#define CONFIG_SYS_PCI_HOLD_DEL	0x20
-
-#define CONFIG_SYS_ROMNAL		15
-#define CONFIG_SYS_ROMFAL		31
-
-#define CONFIG_SYS_REFINT		430
-
-#define CONFIG_SYS_DBUS_SIZE2		1
-
-#define CONFIG_SYS_BSTOPRE		121
-#define CONFIG_SYS_REFREC		8
-#define CONFIG_SYS_RDLAT		4
-#define CONFIG_SYS_PRETOACT		3
-#define CONFIG_SYS_ACTTOPRE		5
-#define CONFIG_SYS_ACTORW		3
-#define CONFIG_SYS_SDMODE_CAS_LAT	3
-#define CONFIG_SYS_SDMODE_WRAP		0
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER	1
-#define CONFIG_SYS_EXTROM			1
-#define CONFIG_SYS_REGDIMM			0
-
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x04000000
-#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
-#define CONFIG_SYS_BANK1_ENABLE	1
-#define CONFIG_SYS_BANK2_START		0x3ff00000
-#define CONFIG_SYS_BANK2_END		0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x3ff00000
-#define CONFIG_SYS_BANK3_END		0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x00000000
-#define CONFIG_SYS_BANK4_END		0x00000000
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x00000000
-#define CONFIG_SYS_BANK5_END		0x00000000
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x00000000
-#define CONFIG_SYS_BANK6_END		0x00000000
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x00000000
-#define CONFIG_SYS_BANK7_END		0x00000000
-#define CONFIG_SYS_BANK7_ENABLE	0
-
-#define CONFIG_SYS_BANK_ENABLE		0x03
-
-#define CONFIG_SYS_ODCR		0x75
-#define CONFIG_SYS_PGMAX		0x32
-
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-#endif	/* __CONFIG_H */