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| author | Dave Gerlach <d-gerlach@ti.com> | 2022-04-08 16:46:50 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-20 11:14:39 -0400 |
| commit | 270f7fd25b3d1e825d3364eee652c3ccc9d5aae4 (patch) | |
| tree | c73f7808c7c6f398dc32ad9caac934e34d203f28 | |
| parent | a96d56572536f02c0d1f09f72bfedfa9cb4ae560 (diff) | |
| download | u-boot-270f7fd25b3d1e825d3364eee652c3ccc9d5aae4.tar.gz u-boot-270f7fd25b3d1e825d3364eee652c3ccc9d5aae4.tar.bz2 u-boot-270f7fd25b3d1e825d3364eee652c3ccc9d5aae4.zip | |
ram: k3-ddrss: Allow use of dt provided initial frequency
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR
frequency that is set for lpddr4 before initialization of the
controller. Make this optional and continue to use PLL bypass frequency
as is done currently if ti,ddr-freq0 is not provided.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| -rw-r--r-- | doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt | 2 | ||||
| -rw-r--r-- | drivers/ram/k3-ddrss/k3-ddrss.c | 15 |
2 files changed, 12 insertions, 5 deletions
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt index df3290a6b9..1ea0a70114 100644 --- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt +++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt @@ -39,6 +39,8 @@ Optional properties: - reg: Must add "ss" to list if the above ss region is included. - ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR by 1/9. +- ti,ddr-freq0: Initial frequency set point, if not provided PLL bypass + frequency will be used. Example (J721E): ================ diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6217f98b33..e8b7aec9e0 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -134,6 +134,7 @@ struct k3_ddrss_desc { struct power_domain ddrdata_pwrdmn; struct clk ddr_clk; struct clk osc_clk; + u32 ddr_freq0; u32 ddr_freq1; u32 ddr_freq2; u32 ddr_fhs_cnt; @@ -223,9 +224,7 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) else if (req_type == 2) clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); else if (req_type == 0) - /* Put DDR pll in bypass mode */ - clk_set_rate(&ddrss->ddr_clk, - clk_get_rate(&ddrss->osc_clk)); + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); else printf("%s: Invalid freq request type\n", __func__); @@ -276,8 +275,7 @@ static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); break; case DENALI_CTL_0_DRAM_CLASS_LPDDR4: - /* Set to bypass frequency for LPDDR4*/ - ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk)); + ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); break; default: ret = -EINVAL; @@ -394,6 +392,13 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev) ddrss->instance = 0; } + ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0); + if (ret) { + ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk); + dev_dbg(dev, + "ddr freq0 not populated, using bypass frequency.\n"); + } + ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); if (ret) dev_err(dev, "ddr freq1 not populated %d\n", ret); |