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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2012-12-05 18:46:04 +0100 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2012-12-06 14:58:57 -0500 |
| commit | 26107309c08f8548a2e0aef0d0aabd64bc2d22c1 (patch) | |
| tree | 195b0d5b03f6b0a78591e71eb397fcb0309dd972 /drivers/ssb | |
| parent | f924e1e989b0bdaf6472668400d67a2142cb6b60 (diff) | |
| download | linux-stable-26107309c08f8548a2e0aef0d0aabd64bc2d22c1.tar.gz linux-stable-26107309c08f8548a2e0aef0d0aabd64bc2d22c1.tar.bz2 linux-stable-26107309c08f8548a2e0aef0d0aabd64bc2d22c1.zip | |
ssb: set the PMU watchdog if available
Some ssb based devices have a PMU and the PMU watchdog register should
be used instead of the register in the chip common part, if the device
has a PMU. This patch also calculates the maximal number the watchdog
could be set to.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb')
| -rw-r--r-- | drivers/ssb/driver_chipcommon.c | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 603b63032e93..6e080f6a07a5 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc) return 20000000; } +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc) +{ + u32 nb; + + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { + if (cc->dev->id.revision < 26) + nb = 16; + else + nb = (cc->dev->id.revision >= 37) ? 32 : 24; + } else { + nb = 28; + } + if (nb == 32) + return 0xffffffff; + else + return (1 << nb) - 1; +} + void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) @@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_chipcommon *cc, /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) { - /* instant NMI */ - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); + u32 maxt; + enum ssb_clkmode clkmode; + + maxt = ssb_chipco_watchdog_get_max_timer(cc); + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { + if (ticks == 1) + ticks = 2; + else if (ticks > maxt) + ticks = maxt; + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks); + } else { + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC; + ssb_chipco_set_clockmode(cc, clkmode); + if (ticks > maxt) + ticks = maxt; + /* instant NMI */ + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); + } } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) |